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  1. V

    stuck at fault

    I have read And I am little bit confused IF B is 1 then how A will become 1 ? f –h –k –L A=1, B=1 H=D, j=0 k=D E=1 L=D
  2. V

    stuck at fault

    yes I can do Q1 IS it path sensitization method to detect fault I think no because path sensitization method to detect path or line fault if one line is fault we detect faulty path I want to learn path sensitization method for Image one suppose C line is faulty how to generate test vector?
  3. V

    stuck at fault

    1.1 = 1 1.0 = 0 0.0 = 0 0.1 = 0 1+1 = 1 1+0 = 1 0+0 = 0 0+1 = 1 1.0 + 1 = 1 0.1 + 1 = 1 0.1 + 0 = 0
  4. V

    stuck at fault

    ok look this A B C D Z ZF 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 Q1 IS it path sensitization method to detect fault
  5. V

    stuck at fault

    look this table A B C D Z Zf 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 test vector for s-a-0 A B C D Z ZF 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0...
  6. V

    stuck at fault

    ok look this if A=1 , B=1, C=1 D=0 Z=AB+CD=1*1+1*0=1+0=1 Zf=AB+D=1*1+0=1+0=1
  7. V

    stuck at fault

    which section is wrong I think output Z and ZF I want to determine test vector that cover maximum fault look Image 1st Fault-free function z = AB+CD Faulty function zf = AB stuck at s-a-0 ,so C must be set to 1 we know the one vector C =1 Q. If we know the C , can we determine D ? there...
  8. V

    stuck at fault

    look this table which test vector is used to cover fault A B C D z zf 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 1 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 0
  9. V

    stuck at fault

    I did not understand z = AB+CD z= output of circuit Q how do you know that C is correct but AB+D is faulty? A B C D Z ZF 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 0...
  10. V

    stuck at fault

    hello I would like to know how we can analyze the fault using look at this pdf file I Image 1st Fault-free function z = AB+CD Faulty function zf = AB Fault-free function z = AB+CD Faulty function zf = AB+D Q1 how we will know that function AB is faulty and function AB+D is faulty? Q2 how to...
  11. V

    Is unix a real time operating ?

    I am not demanding, don't angery , thanks to all member they all always help me lots
  12. V

    Is unix a real time operating ?

    look at post #12 I have read some material and tried on google THen I have written some short nots
  13. V

    Is unix a real time operating ?

    this is different post.. here I have written short notes about how rtos are different from general operating system
  14. V

    Is unix a real time operating ?

    Both Windows and Unix can not work as real time operating system. whats the reason why can't they do this I mean what is difference between general os and rtos in terms of hardware and software design
  15. V

    Is unix a real time operating ?

    look at this pdf file there are two statement unix as real time operating system and window as real time operating system I don't understand what is the meaning of both statement in this pdf file can someone tell me what is this ?
  16. V

    charge carrier transport in semiconductor

    there are two type of charge carrier in semiconductor , one is electron which carry negative charge and other is hole which carry positive charge and generate electron hole pair carrier transport means the motion of two charge carrier what is carrier statics in semiconductor ?
  17. V

    automatic test pattern generation

    how does test vector generate manually ?
  18. V

    built in self test

    I think built in self test is used to test memory and connection in circuit memory BIST LOGIC BIST just for example , we made micro controller circuit . If decoder circuit in microcontroller is faulty , how does circuit detect fault by self checking that decoder is faulty ? I think we need...
  19. V

    automatic test pattern generation

    I think its software that generate test vector ATPG tool like cadence ATPG tools checks if the design is capable to perform the test according to the settings, then it generates test vector according to statement software is used to determine test vector I have done little work on...
  20. V

    automatic test pattern generation

    VLSI device are tested by automatic test equipment that perform verity of test VLSI design are automated. automatic test pattern generation is design automation process used to find test vector I don't understand how the test vector generate automatically. can someone help ?
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