I expect that sooner or later Xilinx will add decompression hardware to the
FPGAs themselves to take advantage of that (significant!) gain you're
seeing... they already have some versions that decrypt the bitstream, as I
recall, adding decompression to that seems pretty straightforward.
---Joel
They already have a bitstream compression option that relies on
bitstream blocks being identical, so the can load the same data into
multiple clb's. In real life, that usually happens when they're all
zeroes, ie for unused hunks of chip. That saves 10-20% typically, but
it probably doesn't compound with my zeroes compression.
Some more elegant decompression would be cool. On the pc side, we
don't care if it would take another second or so to compress the
bitstream; hell, the Xilinx software should do it for us! They could
make the entire thing transparent.
The idea of an 80 megabit config stream gives me the creeps.
John