Hi guys,
I have a motor controller that uses the SG3524 chip to generate a PWM pulse. This is sent to mosfet drivers which run an H bridge setup.
The onbard current limiting is resulting in a "jerkiness" of the motor when it starts to hit the 0.2v limit on the CL + pin of the SG3524.
The current limiting in the SG3524 is supposed to reduce the duty cycle to 25% as the CL+ pin reaches 0.2v and then further to 0% when it goes above 0.2v.
I figure that because a motor controller is going to drop the current as soon as the limiter cuts the PWM duty cycle back, the "jerkiness" is from the duty cycle being dropped to 0%, and the current limiting turning off, then turning the pulse train back on, resulting in a high current, resulting in the duty cycle dropping to 0% again, and so on.
I was wondering if anyone had any suggestions for a way to provide some way of smoothing this out?
Any ideas much appreciated.
I have a motor controller that uses the SG3524 chip to generate a PWM pulse. This is sent to mosfet drivers which run an H bridge setup.
The onbard current limiting is resulting in a "jerkiness" of the motor when it starts to hit the 0.2v limit on the CL + pin of the SG3524.
The current limiting in the SG3524 is supposed to reduce the duty cycle to 25% as the CL+ pin reaches 0.2v and then further to 0% when it goes above 0.2v.
I figure that because a motor controller is going to drop the current as soon as the limiter cuts the PWM duty cycle back, the "jerkiness" is from the duty cycle being dropped to 0%, and the current limiting turning off, then turning the pulse train back on, resulting in a high current, resulting in the duty cycle dropping to 0% again, and so on.
I was wondering if anyone had any suggestions for a way to provide some way of smoothing this out?
Any ideas much appreciated.
