Reset asynchronous assertion and synchronous deassertion

[arant]

Hi Eveyone,

The specifications goes something like this :

The device core asserts reset to the device peripherals asynchronously
and releases (deasserts) the reset synchronously after 4 clock periods

there are two possible implementations for the above spec which one is
better :

signal reset_reg : std_logic_vector(3 downto 0);

p_reset_reg : process(clk,reset_async)
begin
if (reset_async = '0') then
-- on async reset assertion reset the registers
reset_reg <= (others => '0');

elsif (clk'event and clk = '1') then

reset_reg(0) <= '1';

reset_shift_reg : for i in (reset_reg'LOW to reset_reg'HIGH -1) loop
reset_reg(i+1) <= reset_reg(i);
end loop reset_shift_reg;

end if ;
end process p_reset_reg;

-- implementation 1 direct assignment of register value to reset_out

reset_out <= reset_reg(3);

-- implementation 2 assignment of decoded value of the register
-- bank to the reset out only when all the four registers attain
-- '1' then release reset to the device

reset_out <= reset_reg(0) and reset_reg(1) and reset_reg(2) and
reset_reg(3);

"I think the second implementation reduces the problem of metastability
at the reset_out as it is less probable that ll the four flops go
metastable at the same time"

Is the above statement (" I think ... time") valid

awaiting your replies