John said:krw wrote:
krw wrote:
[...]
b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)
So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.
Dead-bugged on top of it with liquid nails glue ...?
Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.
You never split gate or opamp sections between sheets?
Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.
Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
John said:krw wrote:
krw wrote:
[...]
b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)
So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.
Dead-bugged on top of it with liquid nails glue ...?
Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.
You never split gate or opamp sections between sheets?
Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.
Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?
John
480)460-2350 Fax: Available upon request | Brass Rat |480)460-2350 Fax: Available upon request | Brass Rat |FatBytestard said:
Jim said:
John said:Nope. Only exception is simple logic gates but even then you'd almostJohn said:krw wrote:
krw wrote:
[...]
b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)
So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.
Dead-bugged on top of it with liquid nails glue ...?
Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.
You never split gate or opamp sections between sheets?
have to twist my arm.
Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?
480)460-2350 Fax: Available upon request | Brass Rat |480)460-2350 Fax: Available upon request | Brass Rat |"A" for "assembly". In the USAF, ALL the schematics are hierarchial. The
John said:John Larkin wrote:
krw wrote:
krw wrote:
[...]
b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)
So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.
Dead-bugged on top of it with liquid nails glue ...?
Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.
You never split gate or opamp sections between sheets?
Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.
I never do hierarchical schematics. Everything's flat.
Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?
Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.
John said:
John said:[...]
I never do hierarchical schematics. Everything's flat.
Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?
Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.
I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?
Yes, it just starts with the next available number at block 1, then goes
on to block 2 and so on until all sub-sheets are done. For proper
documentation you must let it print out all 16 blocks, otherwise a
technician could never repair the unit. For a design review you don't
necessarily have to (in med or aero and such you usually do).
There are tons of other options for numbering but since many of my
larger designs get renumbered anyhow I don't care that much. As long as
the CAD doesn't screw up multi-device chips like gEDA does.
Field service needs all 16 sub-module pages. It has to be that way on
any design because R325 will be R291 on the previous channel. Unless the
sub-modules are separate little boards stuck into a big one but then
they'd be another assy number.
480)460-2350 Fax: Available upon request | Brass Rat |Oh, and Cadsoft Eagle? Hasn't crashed in years, since the first day I
fired it up. That's what I expect from CAD and that's how it ought to
be, as far as I am concerned. And being self-employed I vote with my
wallet on this stuff
John said:krw wrote:
krw wrote:
[...]
b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)
So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.
Dead-bugged on top of it with liquid nails glue ...?
Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.
You never split gate or opamp sections between sheets?
Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.
Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?
John said:John Larkin wrote:
krw wrote:
krw wrote:
[...]
b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)
So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.
Dead-bugged on top of it with liquid nails glue ...?
Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.
You never split gate or opamp sections between sheets?
Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.
I never do hierarchical schematics. Everything's flat.
Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?
Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.
I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?
