[krw]

John Larkin wrote:
John Larkin wrote:

[...]

I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?

Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.

I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Yes, it just starts with the next available number at block 1, then goes
on to block 2 and so on until all sub-sheets are done. For proper
documentation you must let it print out all 16 blocks, otherwise a
technician could never repair the unit. For a design review you don't
necessarily have to (in med or aero and such you usually do).

We're planning on setting the service and test departments up with
schematic viewers so they can use the hierarchy.

There are tons of other options for numbering but since many of my
larger designs get renumbered anyhow I don't care that much. As long as
the CAD doesn't screw up multi-device chips like gEDA does.

We tend to start numbering from xx01 on each sheet, with duplicate
sheets having the same low order numbers.

 

[Joerg]

]

Oh, and Cadsoft Eagle? Hasn't crashed in years, since the first day I
fired it up. That's what I expect from CAD and that's how it ought to
be, as far as I am concerned. And being self-employed I vote with my
wallet on this stuff

Nothing else on my work computer crashes regularly, except Capture.

I can add one that crashes more, on all computers here: Adobe Acrobat
Reader. But I guess everyone knows that.

[...]

 

[Joerg]

John Larkin wrote:
John Larkin wrote: [...]

I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?

Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.

I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Yes, it just starts with the next available number at block 1, then goes
on to block 2 and so on until all sub-sheets are done. For proper
documentation you must let it print out all 16 blocks, otherwise a
technician could never repair the unit. For a design review you don't
necessarily have to (in med or aero and such you usually do).

There are tons of other options for numbering but since many of my
larger designs get renumbered anyhow I don't care that much. As long as
the CAD doesn't screw up multi-device chips like gEDA does.

How do you print the schematic for field service? Where the hell is
R325 in one of the instances when only one sub-module schematic
exists?

Field service needs all 16 sub-module pages. It has to be that way on
any design because R325 will be R291 on the previous channel. Unless the
sub-modules are separate little boards stuck into a big one but then
they'd be another assy number.

In PSpice you can have schematic "instances". I don't use it because
I do chips, so each repeated hierarchical block can reference the same
schematic. But a PCB-based designer would use either "instances" or
simply repeat pages (copy), which would generate individual reference
designators.

Yep, you's guys can get away with just placing the blocks. That's also
how the chip designs went where I was involved. This is because it
rarely happens that a technician has to swap a FET inside a chip ;-)

 

[Joerg]

John Larkin wrote:
John Larkin wrote: [...]

I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?

Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.

I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Yes, it just starts with the next available number at block 1, then goes
on to block 2 and so on until all sub-sheets are done. For proper
documentation you must let it print out all 16 blocks, otherwise a
technician could never repair the unit. For a design review you don't
necessarily have to (in med or aero and such you usually do).

We're planning on setting the service and test departments up with
schematic viewers so they can use the hierarchy.

Hey, did you start modernizing the place? When I did that the first time
it was met with quite a bit of resistance. Until they started feeling
the benefits. "How did you get that stock room quantity?" ... "From my
computation machine." ... "Oh."

[...]

 

[Joerg]

Jim Thompson wrote:
On Thu, 06 Aug 2009 07:42:46 -0700, John Larkin

[snip]
I never do hierarchical schematics. Everything's flat.

John
I _always_ do hierarchical schematics! Each block is a functional
cell, making it easier for my layout guy to sort out signal and power
routing. And for me to simulate pieces before combining into the
total chip.

T'is how it ought to be. Just MHO.
Yes, and I think it'll reduce our errors significantly. However, I've
just run into another OrCad gotcha. Named signals get ruined when
buried in a hierarchy.
In PSpice Schematics "appending" a page number is an option. But
you're probably using Crapture :-(

Reading you occasional comments about PSpice schematics it sounds like
it must be the best thing since pivot irrigation. Why don't they sell it
stand-alone, sans SPICE? There is a serious market out there.

[...]

I believe it's a freebie off the web somewhere(*). It doesn't require
a license. OrCAD only includes it on demand... like me, I refuse
updates unless Schematics is included.

(*) Look for student or evaluation versions... v8 is best, before
OrCAD hobbling ;-)

I'll give it a shot. But for biz you'll probably have to buy it
someplace. It's a pity that older schematic editors aren't available
(except with Cadsoft Eagle, I think they still offer all the versions
back to caveman). Mechanical CAD is different, I bought a license at a
liquidator for a song, installed, went to registration, crossed my
fingers and then to my utter amazement the unlock code trickled in.

 

[krw]

]

Oh, and Cadsoft Eagle? Hasn't crashed in years, since the first day I
fired it up. That's what I expect from CAD and that's how it ought to
be, as far as I am concerned. And being self-employed I vote with my
wallet on this stuff

Nothing else on my work computer crashes regularly, except Capture.

I can add one that crashes more, on all computers here: Adobe Acrobat
Reader. But I guess everyone knows that.

[...]

 

[John Larkin]

John Larkin wrote:
John Larkin wrote:
krw wrote:
krw wrote:
[...]


b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)

So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.

Dead-bugged on top of it with liquid nails glue ...?


Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.

You never split gate or opamp sections between sheets?

Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.


I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff

What happens to reference designators in a hierarchical schematic?


Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.

I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Capture renumbers - flat - them for each instance.

How do you print the schematic for field service? Where the hell is
R325 in one of the instances when only one sub-module schematic
exists?

They all exist. You print all the sheets. Ugly as hell, but it's
really not much worse than flat schematics. Much better if you use a
viewer.

Then the hierarchical thing doesn't seem to be much different than
just doing it flat.

John

 

[krw]

John Larkin wrote:
John Larkin wrote:
John Larkin wrote:
[...]

I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?

Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.

I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Yes, it just starts with the next available number at block 1, then goes
on to block 2 and so on until all sub-sheets are done. For proper
documentation you must let it print out all 16 blocks, otherwise a
technician could never repair the unit. For a design review you don't
necessarily have to (in med or aero and such you usually do).

We're planning on setting the service and test departments up with
schematic viewers so they can use the hierarchy.

Hey, did you start modernizing the place? When I did that the first time
it was met with quite a bit of resistance. Until they started feeling
the benefits. "How did you get that stock room quantity?" ... "From my
computation machine." ... "Oh."

If I have anything to do with it... They already have the PCs, but
use them to view PDFs.

I think I finally got them to understand that engineering really needs
prices. Sometime in the future they're going to dump the purchasing
database into the parts database once a month. It's a start.
Quantity?

[...]

Next issue: how do you deal with multiple SKUs built off the same
schematics? They want us to manually edit the schematics for service.
I'm trying to convince them that they really don't want to do that. I
certainly don't want to be held responsible for multiple versions of
the same data.

 

[krw]

John Larkin wrote:
John Larkin wrote:
krw wrote:
krw wrote:
[...]


b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)

So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.

Dead-bugged on top of it with liquid nails glue ...?


Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.

You never split gate or opamp sections between sheets?

Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.


I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff

What happens to reference designators in a hierarchical schematic?


Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.


I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Capture renumbers - flat - them for each instance.

How do you print the schematic for field service? Where the hell is
R325 in one of the instances when only one sub-module schematic
exists?

They all exist. You print all the sheets. Ugly as hell, but it's
really not much worse than flat schematics. Much better if you use a
viewer.

Then the hierarchical thing doesn't seem to be much different than
just doing it flat.

If the most important thing in life is the cost of printer paper, you
may have a point. OTOH, hierarchies are easier to understand,
simulate, and reuse; sorta the point of schematics.

 

[FatBytestard]

No, top of the line name-brand 'puters. When more demanding apps such as
SPICE, SolidWorks or AutoCad don't crash that is kind of a sign that
there's a wee problem with the SW I'd think.

Or perhaps not knowing that there were things that required setting up.

 

[FatBytestard]

Oh, and Cadsoft Eagle? Hasn't crashed in years, since the first day I
fired it up. That's what I expect from CAD and that's how it ought to
be, as far as I am concerned. And being self-employed I vote with my
wallet on this stuff

Few Linux apps crash. That doesn't magically make it a robust app,
however. Wallet or not. Time has a price as well, and mine ain't cheap.

 

[life imitates life]

And you folks bitch about top posting when we've got to paw through four
pages of 8-deep quoted lines to get to a (mostly useless) one line response?
Can we say "snip"?

If you are so goddamned retarded that you do not know how to navigate a
computer rendered page(s) of text via cursor keys, you should not only
not be in Usenet, you should not be at a console, especially if there is
money involved.

Since I find it hard to believe that you do not know what the **** a
cursor key is, SHUT THE **** UP, you crybaby motherfucker.

Learn to hit page down. Learn to place your retarded responses ate the
BOTTOM. You know, chronologically formatted.

And yes, YOU can snip whenever YOU want to, and WE can CHOOSE to do so
or NOT. Just like it ever was.

I cannot believe that after all these years, your skull is STILL THREE
INCHES THICK!!!

It ain't email, dipshit. The reason for chrono is for OTHERS that are
not in the thread, and did not read the whole thread. In many cases,
other posts in a thread are not even available to the reader.

So get off your little high hobby horsey, little boy, and catch up with
the rest of the world.

 

[John Larkin]

On Fri, 07 Aug 2009 15:52:56 -0700, John Larkin

John Larkin wrote:
John Larkin wrote:
krw wrote:
krw wrote:
[...]


b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)

So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.

Dead-bugged on top of it with liquid nails glue ...?


Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.

You never split gate or opamp sections between sheets?

Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.


I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff

What happens to reference designators in a hierarchical schematic?


Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.


I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Capture renumbers - flat - them for each instance.

How do you print the schematic for field service? Where the hell is
R325 in one of the instances when only one sub-module schematic
exists?

They all exist. You print all the sheets. Ugly as hell, but it's
really not much worse than flat schematics. Much better if you use a
viewer.

Then the hierarchical thing doesn't seem to be much different than
just doing it flat.

If the most important thing in life is the cost of printer paper, you
may have a point. OTOH, hierarchies are easier to understand,
simulate, and reuse; sorta the point of schematics.

Somehow I don't have trouble understanding 16 sheets that are labeled
CHANNEL 0 through CHANNEL 15, each with all the reference designators
and connector pins in plain view.

John

 

[FatBytestard]

I can add one that crashes more, on all computers here: Adobe Acrobat
Reader. But I guess everyone knows that.

[...]

Mine is all updated, and has NEVER crashed.

When you attempt to print a large pdf, you should locally spool the
print job first. If you do not know how to set your printer/computer up
to spool properly, you deserve to have crashes until someone guides you
through the process.

Operator error... again.

 

[Charlie E.]

That sets up the netlist, but how do I use that information within
Capture itself? My issue is (or was, I already did it the hard way)
creating differential pairs out of signals down in the hierarchy. It
has to be done from the flat nets dialogs and there is no hierarchy
information there.

Don't know for sure. What release are you on? Unfortunately, I only
have 10.3 to work with, and I think they added diff pair support
around 16.0...

Charlie

 

[krw]

Don't know for sure. What release are you on? Unfortunately, I only
have 10.3 to work with, and I think they added diff pair support
around 16.0...

I'm using Capture 15.7, but the "diff pair" support is pretty much
just another property (though is only editable in flat nets view).
We're then using Allegro 16.0 for the layout. It does reuse and diff
pairs, or so I'm told.

 

[krw]

On Fri, 07 Aug 2009 15:52:56 -0700, John Larkin

John Larkin wrote:
John Larkin wrote:
krw wrote:
krw wrote:
[...]


b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)

So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.

Dead-bugged on top of it with liquid nails glue ...?


Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.

You never split gate or opamp sections between sheets?

Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.


I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff

What happens to reference designators in a hierarchical schematic?


Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.


I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Capture renumbers - flat - them for each instance.

How do you print the schematic for field service? Where the hell is
R325 in one of the instances when only one sub-module schematic
exists?

They all exist. You print all the sheets. Ugly as hell, but it's
really not much worse than flat schematics. Much better if you use a
viewer.

Then the hierarchical thing doesn't seem to be much different than
just doing it flat.

If the most important thing in life is the cost of printer paper, you
may have a point. OTOH, hierarchies are easier to understand,
simulate, and reuse; sorta the point of schematics.

Somehow I don't have trouble understanding 16 sheets that are labeled
CHANNEL 0 through CHANNEL 15, each with all the reference designators
and connector pins in plain view.

And nothing would change if those sixteen sheets were instances of a
hierarchical block, except you'd have another higher level block that
would show their interconnect. IOW, more information.

 

[Jim Thompson]

I'm using Capture 15.7, but the "diff pair" support is pretty much
just another property (though is only editable in flat nets view).
We're then using Allegro 16.0 for the layout. It does reuse and diff
pairs, or so I'm told.

I'm puzzled. What IS "diff pair" support?

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine Sometimes I even put it in the food

 

[TheJoker]

...or so I'm old.

Hehehehe...

 

[krw]

I'm puzzled. What IS "diff pair" support?

It essentially is a way to mark the wires as a pair so the router can
use, and DRC check, the appropriate wiring rules.