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Kevin Weddle
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Posts posted by Kevin Weddle
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A center tapped transformer is perfect for producing a negative dc supply voltage. This one doesn't have one.
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At 1cycle/3s the slew rate is probably too low to double the voltage. The 5kHz variation stopped working, probably it's a bad inverter. Don't have another one.
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The original circuit. The voltmeter shows a positive voltage on the positive cycle always 300mV.
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It's the charge and discharge on the capacitor. A discharged capacitor doesn't have to discharge, a charged capacitor has to discharge.
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It's a CMOS inverter oscillator. The voltage will double, then the inverter will fail.
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I finished the circuit. It is uses two inverters, capacitors, and resistors. The resistors pull up and the output is about a cycle every few seconds. There isn't a gate resistor connected to ground.
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I do not know what you mean when you say "0V sink current" and "nothing to output high".
The difference between the TTL and CMOS inverter oscillator if I recall is the CMOS inverter following the feedback capacitor needed a gate discharge resistor. The TTL circuit used a pullup instead of pull down resistor for this difference. Was I missing the gate discharge resistor? -
I'm designing a simple inverter oscillator. There are one or two designs depending on if the logic is bipolar transistor or fet. Is it the bipolar transistor logic which requires a 0v sink current? Does the fet logic only require nothing to output high?
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Can field effect transistors be used at a very low current in a common drain amplifier?The source resistance is very low and a high reverse VGS is used.
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I guessed at the low impedance load part. The JFEt circuit uses a high current 0VGS instead of a low current 0VGS. If it's similar to a MOSFET, the transconductance is higher. Is a higher transconductance always better? Aside from the fact that there are gain setting resistors which make the VGS signal loss negligible.
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Kevin, the improved and fixed project uses opamps with PNP bipolar transistor inputs, not Jfet inputs so that they work with an input voltage as low as the negative supply voltage.
The input voltage of opamp U2 goes from 0V (its negative supply voltage) to +11.2V and never goes as high as the positive supply where it will have its output saturated as high as it can go.
Recently I used a JFET in a small circuit. The gm specification recommended is around 0VGS at 15V VDS. I used a very low value source resistor and drain resisitor for gain. Should they be good for low resistance loads? -
The voltages and currents aren't what they should be then. You can make a cheap power supply. This is a 30V stabilized power supply. Either the pot or the transistors used are now of out of specification.
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oh yeah. how about that.
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WinDTrek, you are on loose ground.
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A polyester capacitor is very cheap.
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Current specifications aren't used much for diodes unless they're exceeded. Jfets have the input connected to the channel. The substate is shorted to the source.
I'll edit this post. Only MOS field effect transistors have their substrate shorted to the source most often. Jfets are biased with a reverse bias gate to drain voltage, or else it conducts Idss at 0VGS. An interesting fact is that because of the reverse bias gate to drain voltage. the source current is a little less. -
Jfet input opamps are a great improvement because they are square law devices. Their input voltage needs to be very close to the supply voltage based on Jfet VGS. Maybe 5V less. Does this opamp need a transistor bias voltage so that the bias impedance is higher than would be a resistor.
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Xristocrat. Tell us what you mean by your earlier posts. What is the design?
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Xristost, I like the stabilized 30v power supply you work on. So many people want a constant voltage...
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ohm's law. It is the equation from which electronics is derived. I wanted to clamp Q2 but it limits the versatility of the simple variable voltage supply.
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Impedance is slightly different from maxing opamp current. Especially when Q2 handles all the current.
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I modfied this posting.
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I was looking to modify Q2 with a BE diode and a VCE zener and an upstream transistor to drop the voltage for the zener. If Q2 has a low BE operating voltage and the parallel diode doesn't go low impedance, U2 will work fine. It's good to hold Q2 at a constant VCE and VBE. As long as the parallel diode doesn't lose impedance, Q2 can supply adequate current to function Q4 and small signal regulation will only be lost under higher current. But all is not lost if you don't exceed the maximum of U2. The voltage will only follow the small signal.
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audio the gain of U2 should only be a liitle more than 2 for low frequency circuits. Only if the powered circuit is very high frequency will C6 lower the feedback enough.
How this ps unit works??
in Theory articles
Posted
Hello Walid, the circuit you found was I think novice. Q3 is an NPN. Indulis recommends removing the resistors and I agree. The load has to be high impedance. Most versatile regulators need to sink current sometimes.