The output of opamp U1 must go negative in order for D9 to reduce the input of opamp U2 to near 0V when the output is shorted so that the output current is regulated.
To get the same terminology, I'm referring to the rev 7 schematic, where U3 is the current limit control and U1 is the 11.2v ref voltage and U2 is the voltage control. I understand that U3 has to go negative. That's why it's connected to the -1.3v supply. However, U1 does not need to go negative (and its V- is connected to the negative pwr supply output at R7, which is always above ground potential). U1's output is always 11.2v above the negative pwr supply output, so it doesn't need connection to the negative supply.
I'm really a beginner, so don't take this as criticism of the design. It's not, but it looks to me like U1 could have V- pin4 connected to the negative output (as in the rev 7 design), to ground, or to the -1.3v supply (assuming one doesn't exceed the 44v limit). Either of those changes would cause the U1 idle current to skip the current sense resistor R7.
In the rev7 design, it really doesn't matter that idle current flows through the current sense resistor. The current limit voltage at the noninverting input of U3 is only relevant when the current limit is reached, so the fact that that voltage changes (relative to ground) as the current changes isn't important. It will be correct when the P2 set current limit is reached. (I'll note, however, that it makes the current limit pot very slightly nonlinear, due to effects on the offset zero point at R17).
However, I'd like to use the U3 input voltages to display the current limit setting and actual current, so I don't want the CL limit voltage to change as the current changes. I can do that by changing the reference voltage for the CL setting to be based relative to ground, while still leaving V- of U3 connected to -1.3. Further, it might be nice for 0v at the CL pin to correspond to 0mA CL setting. That's a problem since the rev 7 design has current flowing through the R7 sense resistor that isn't flowing through the load connected to the output terminals. The U1 quiescent idle current (2-4 mA, depending on the OA used) flows through R7. Also the 5.6mA used for the D8, R4 vref, the R5-R6 gain resistors around U1 (another ~0.5mA) and the P1 voltage set pot current (another ~1mA) all flow through R7 current sense.
Those last 3 have to go through R7 (although they can be reduced somewhat with design mods), but it looks to me like the U1 quiescent idle current could go directly to ground and bypass R7. If I understand the circuit, the purpose of R17, below the P2 adjust pot is to counteract for those effects that cause the 0 amp CL setting to be above 0v across R7 current sense.
None of this is important unless you want to use the voltage at the input pins of U3 to display the actual current and CL setting, as I do.
As I said,I'm trying to learn, and one way is to try various modifications and try to understand the effects. I could just offset the voltage at my voltmeter (used to display current and CL limit) to null out the quiescent current so that the meter reads zero when the voltage across the R7 sense resistor equals the quiescent current due to those effects described above. I think I can do that by measuring relative to the voltage at the top of R17, which should equal that quiescent current times R7. But I can also just reduce those effects by making them small enough to ignore.
I'm considering eliminating U1 and replacing it with a TL431 which can run at a milliamp or two. That removes the U1 quiescent current, the D8 zener current and the R5-R6 gain resistor current.
Then increasing the resistance of the P1 voltage pot cuts the total current down to levels I can probably ignore. I'm playing with simulating that approach (Multisim) and with just offsetting the quiescent voltage on R7 current sense by measuring voltages relative to R17, not ground. (This may be best).
I freely admit I may be off base here, but I'm learning as I go, and it's fun. I do hope others with more design experience will point out flaws in my thinking, but if they don't, and I end up building something that doesn't work, I'm happy with that, so long as I figure out what went wrong. I can always build version 2. <smile>
