AD8218 spice model is messed up.

[[email protected]]

Could someone verify for me that the AD8218 spice model is screwed up? The model and data sheet are here

http://www.analog.com/en/specialty-amplifiers/current-sense-amplifiers/ad8218/products/product.html

I'm just trying to reproduce Figure 35 in the datasheet. I'm using the circuit in Figure 34. I tied Vs and ENB to +IN because Ltspice doesn't like those pins floating. I set the shunt resistor to 0.02 ohms, the battery voltage to 24V, the reference to 1.25v and vary the Load from -5Amps to 5Amps in 0.05amp increments. My results show the part offsetting by twice the reference voltage instead of the reference voltage. I can reproduce the graph with the 1.25V reference but the datasheet shows a 2.5v reference. Here is thespice netlist.

* C:\Projects\LIT\N48_TEC_Driver\simulation\AD8218Test.asc
XU1 Vpos Vneg Vpos Vref Vpos 0 Vout AD8218
V3 Vpos 0 24
R2 Vneg Vpos 0.02
V1 Vref 0 1.25
I1 N001 0 1
R1 Vneg N001 100
..include AD8218.cir
..dc I1 -5 5 0.05
..backanno
..end

Thanks

 

[[email protected]]

Could someone verify for me that the AD8218 spice model is screwed up? The model and data sheet are here



http://www.analog.com/en/specialty-amplifiers/current-sense-amplifiers/ad8218/products/product.html



I'm just trying to reproduce Figure 35 in the datasheet. I'm using the circuit in Figure 34. I tied Vs and ENB to +IN because Ltspice doesn't like those pins floating. I set the shunt resistor to 0.02 ohms, the battery voltage to 24V, the reference to 1.25v and vary the Load from -5Amps to 5Amps in 0.05amp increments. My results show the part offsetting by twice the reference voltage instead of the reference voltage. I can reproduce the graph with the 1.25V reference but the datasheet shows a 2.5v reference. Here is the spice netlist.



* C:\Projects\LIT\N48_TEC_Driver\simulation\AD8218Test.asc

XU1 Vpos Vneg Vpos Vref Vpos 0 Vout AD8218

V3 Vpos 0 24

R2 Vneg Vpos 0.02

V1 Vref 0 1.25

I1 N001 0 1

R1 Vneg N001 100

.include AD8218.cir

.dc I1 -5 5 0.05

.backanno

.end



Thanks

I think line 129 is wrong

E03 70 0 Value={ IF( V(ENB) == 0, V(65) + V(600) + .08 + V(ref), IF( V(ENB) != 0, V(65) + V(600) + V(ref), V(65) + V(600) )) }

v(ref) is already added in on line 56. I think the line should read.

E03 70 0 Value={ IF( V(ENB) == 0, V(65) + V(600) + .08, V(65) + V(600) ) }

V(ENB) is either equal or not equal to zero, there is no third state and adding the V(ref) is redundant. Changing this line gives me the results I expect. But maybe I'm expecting the wrong results

 

[[email protected]]

Post the actual .asc file.



Grounding pins that should be floated is a no-no.



I use a part I made called NoFloat which applies a resistor of value

{1/Gmin} to ground.



...Jim Thompson

--

| James E.Thompson | mens |

| Analog Innovations | et |

| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |

| San Tan Valley, AZ 85142 Skype: Contacts Only | |

| Voice480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |



I love to cook with wine. Sometimes I even put it in the food.

Here is the ascii file.

Version 4
SHEET 1 1220 680
WIRE 272 -48 240 -48
WIRE 288 -48 272 -48
WIRE -96 -16 -192 -16
WIRE 64 -16 -16 -16
WIRE 1072 16 976 16
WIRE 1216 16 1072 16
WIRE 976 112 976 16
WIRE 64 128 64 -16
WIRE 112 128 64 128
WIRE 160 128 112 128
WIRE 240 128 240 -48
WIRE 288 128 288 -48
WIRE -192 144 -192 -16
WIRE 64 160 64 128
WIRE 160 160 160 128
WIRE 192 160 160 160
WIRE 480 192 352 192
WIRE 640 192 480 192
WIRE 192 224 160 224
WIRE 64 256 64 240
WIRE 128 256 64 256
WIRE 160 256 160 224
WIRE 160 256 128 256
WIRE 976 304 976 192
WIRE -192 320 -192 224
WIRE 240 352 240 256
WIRE 352 352 240 352
WIRE 464 352 352 352
WIRE 64 384 64 256
FLAG 288 256 0
FLAG 64 464 0
FLAG 480 192 Vout
FLAG 112 128 Vneg
FLAG 128 256 Vpos
FLAG 976 304 0
FLAG 1072 16 Vref
FLAG 272 -48 Vpos
FLAG 352 352 Vref
FLAG -192 320 0
SYMBOL Opamps\\AD8218 224 192 R0
SYMATTR InstName U1
SYMATTR SpiceModel AD8218
SYMBOL voltage 64 368 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 24
SYMBOL res 48 144 R0
SYMATTR InstName R2
SYMATTR Value 0.02
SYMBOL voltage 976 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.50
SYMBOL current -192 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value 1
SYMBOL res 0 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100
TEXT 456 432 Left 2 !.include AD8218.cir
TEXT 448 392 Left 2 !.dc I1 -5 5 0.05

 

[[email protected]]

Looks like your first observation is correct... the model is certainly

messed up... no surprise... Spice modeling at Analog Devices is

managed under marketing :-(



I tried patching the model, but couldn't make it play.



Does the actual part behave like expressed on the data sheet? If so,

maybe I can write a proper model.



...Jim Thompson

--

| James E.Thompson | mens |

| Analog Innovations | et |

| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |

| San Tan Valley, AZ 85142 Skype: Contacts Only | |

| Voice480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |



I love to cook with wine. Sometimes I even put it in the food.

I don't have the actual part. I'm giving up on it and switching to the LT6016.

Thanks for the help.

 

[[email protected]]

I need an AD8218 symbol... AD8218.asy











































































...Jim Thompson

--

| James E.Thompson | mens |

| Analog Innovations | et |

| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |

| San Tan Valley, AZ 85142 Skype: Contacts Only | |

| Voice480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |



I love to cook with wine. Sometimes I even put it in the food.

Here is the symbol.

Version 4
SymbolType CELL
LINE Normal -32 72 124 0
LINE Normal -32 -79 -32 72
LINE Normal 124 0 -32 -79
LINE Normal 64 -30 64 -60
LINE Normal 64 27 64 61
LINE Normal 16 50 16 60
LINE Normal 16 -56 16 -60
LINE Normal 16 -55 16 -56
TEXT 71 -46 Left 2 +
TEXT 75 46 Left 2 -
TEXT -26 33 Left 2 +
TEXT -26 -34 Left 2 -
WINDOW 0 16 -80 Left 2
SYMATTR SpiceModel
SYMATTR Prefix X
SYMATTR Description
SYMATTR Value2
SYMATTR SpiceLine
SYMATTR SpiceLine2
SYMATTR ModelFile
PIN -32 32 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 1
PIN -32 -32 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN 64 -64 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 3
PIN 16 64 BOTTOM 15
PINATTR PinName ref
PINATTR SpiceOrder 4
PIN 16 -64 TOP 15
PINATTR PinName enb
PINATTR SpiceOrder 5
PIN 64 64 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 6
PIN 128 0 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 7

 

[Fred Abse]

V(ENB) is either equal or not equal to zero, there is no third state and
adding the V(ref) is redundant. Changing this line gives me the results I
expect. But maybe I'm expecting the wrong results

Doesn't make it work for me. With + and - inputs strapped, and a common
mode stepped voltage applied, and a 2.5V Vref, offset is 2.5V, up to 5.6V
applied, then jumps to 5.2V.

Unused inputs grounded via 1T resistors, to make the solver happy.

"if" syntax differs between Pspice and LTspice. That may have something to
do with it.

AD is a TI subsidiary, now. I wonder if that subcircuit behaves properly
in TINA?

If I get the time, I'll draw the subcircuit out as a schematic. I find
that's the easiest way of debugging.

 

[Joerg]

Doesn't make it work for me. With + and - inputs strapped, and a common
mode stepped voltage applied, and a 2.5V Vref, offset is 2.5V, up to 5.6V
applied, then jumps to 5.2V.

Unused inputs grounded via 1T resistors, to make the solver happy.

"if" syntax differs between Pspice and LTspice. That may have something to
do with it.

AD is a TI subsidiary, now. ...

WHAT? Seriously? When did that happen?

[...]

 

[Fred Abse]

Doesn't make it work for me. With + and - inputs strapped, and a common
mode stepped voltage applied, and a 2.5V Vref, offset is 2.5V, up to
5.6V applied, then jumps to 5.2V.

Unused inputs grounded via 1T resistors, to make the solver happy.

"if" syntax differs between Pspice and LTspice. That may have something
to do with it.

AD is a TI subsidiary, now. ...

WHAT? Seriously? When did that happen?

[...]

I was confusing them with Burr Brown.

They appear to be one of the few remaining independents.

Sorry,pardon.

 

[Joerg]

On Fri, 19 Jul 2013 11:56:10 -0700, wanderer wrote:

V(ENB) is either equal or not equal to zero, there is no third state
and adding the V(ref) is redundant. Changing this line gives me the
results I expect. But maybe I'm expecting the wrong results
Doesn't make it work for me. With + and - inputs strapped, and a common
mode stepped voltage applied, and a 2.5V Vref, offset is 2.5V, up to
5.6V applied, then jumps to 5.2V.

Unused inputs grounded via 1T resistors, to make the solver happy.

"if" syntax differs between Pspice and LTspice. That may have something
to do with it.

AD is a TI subsidiary, now. ...

WHAT? Seriously? When did that happen?

[...]

I was confusing them with Burr Brown.

They appear to be one of the few remaining independents.

Sorry,pardon.

Whew. Don't give us such as scare again this early in the morning

TI swallowed a lot of companies. Burr-Brown, Unitrode, and then National
Semiconductor. I hope there won't be much more consolidation because
that reduces our options. Or at least if there is, then there should be
new players coming up.

 

[Fred Abse]

(These should work just fine in LTspice, as well as in any other Spice
variant which adheres to Berkeley Spice basics... except some may need
a name change to a "B" source... I think LTspice handles both
syntaxes.)

LTspice handles quite a few syntaxes (syntaces?) that aren't in the manual.

The nice thing about standards is that there are so many to choose from...

 

[Joerg]

LTspice handles quite a few syntaxes (syntaces?) that aren't in the manual.

I think syntaxes is right. But it sound too much like sin taxes.

[...]

 

[Fred Abse]

I think syntaxes is right. But it sound too much like sin taxes.

Only in certain counties in Nevada...

 

[[email protected]]

Could someone verify for me that the AD8218 spice model is screwed up? The model and data sheet are here



http://www.analog.com/en/specialty-amplifiers/current-sense-amplifiers/ad8218/products/product.html



I'm just trying to reproduce Figure 35 in the datasheet. I'm using the circuit in Figure 34. I tied Vs and ENB to +IN because Ltspice doesn't like those pins floating. I set the shunt resistor to 0.02 ohms, the battery voltage to 24V, the reference to 1.25v and vary the Load from -5Amps to 5Amps in 0.05amp increments. My results show the part offsetting by twice the reference voltage instead of the reference voltage. I can reproduce the graph with the 1.25V reference but the datasheet shows a 2.5v reference. Here is the spice netlist.



* C:\Projects\LIT\N48_TEC_Driver\simulation\AD8218Test.asc

XU1 Vpos Vneg Vpos Vref Vpos 0 Vout AD8218

V3 Vpos 0 24

R2 Vneg Vpos 0.02

V1 Vref 0 1.25

I1 N001 0 1

R1 Vneg N001 100

.include AD8218.cir

.dc I1 -5 5 0.05

.backanno

.end



Thanks

I received a reply from Analog Devices

"I think we can acknowledge the error in the model. I will have the engineer that created the model fix the error
and have the corrected version up on the web within the week."

 

[RobertMacy]

[snip]

Seems clear that ADI is not going to produce a revised Spice model as
promised.

So... does anyone have an AD8218 device at hand and could make a few
measurements? Not covered or vaguely defined in the data sheet...

(1) What is the potential of Vs (pin 2) when no external supply is
attached? (+IN & -IN both at +5V)

(2) What is the potential on ENB (pin 3) when floating?

(3) What is the potential on REF (pin 7) when ENB is grounded and no
external reference is applied?

(4) What is the potential on REF (pin 7) when ENB is floating and no
external reference is applied?

(5) What potential is on OUT (pin 5) when ENB is grounded _and_ REF
(pin 7) has 2.5V applied? (+IN & -IN both at +5V)

If I can get the above information I'll write my own model... many
fewer lines than the 157 lines of the ADI-provided model >:-}

...Jim Thompson

Did you send an email to Alex Bordodynov?

 

[wanderer]

Could someone verify for me that the AD8218 spice model is screwed up? The model and data sheet are here



http://www.analog.com/en/specialty-amplifiers/current-sense-amplifiers/ad8218/products/product.html



I'm just trying to reproduce Figure 35 in the datasheet. I'm using the circuit in Figure 34. I tied Vs and ENB to +IN because Ltspice doesn't like those pins floating. I set the shunt resistor to 0.02 ohms, the battery voltage to 24V, the reference to 1.25v and vary the Load from -5Amps to 5Amps in 0.05amp increments. My results show the part offsetting by twice the reference voltage instead of the reference voltage. I can reproduce the graph with the 1.25V reference but the datasheet shows a 2.5v reference. Here is the spice netlist.



* C:\Projects\LIT\N48_TEC_Driver\simulation\AD8218Test.asc

XU1 Vpos Vneg Vpos Vref Vpos 0 Vout AD8218

V3 Vpos 0 24

R2 Vneg Vpos 0.02

V1 Vref 0 1.25

I1 N001 0 1

R1 Vneg N001 100

.include AD8218.cir

.dc I1 -5 5 0.05

.backanno

.end



Thanks

I received the new AD8218.cir file. I haven't tried it yet. It should be onthe ADI website within the next week or so.

* AD8218 SPICE Macro-model
* Description: Current Shunt Monitor, high side current sensing
* Generic Desc: 4.0V to 80V operation, 8S6DPTMRNJIX
* Developed by: DK
* Revision History:
* 1.0 (9/2012) - DK - initial release
* 2.0 (8/2013) - PB - modified gain of voltages on VREF to output from 2x to 1x

* Copyright 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/s...nTools/spiceModels/license/spice_general.html
* for License Statement. Use of this model indicates your acceptance
* of the terms and provisions in the License Statement.
*
*
* Not Modeled:
* Temperature effects
* PSRR vs Frequency
*
* Parameters modeled include:
* CMRR vs Frequency
* VOS (RTI)
* Bandwidth
* Gain Error
* Voltage Spectral Noise: 110nV/rt hz at 1kHz
* Output Impedance: 2 ohms
* Slew Rate
* Common Mode Range: 4.0V to 80V
*
* END Notes
* Maximum output voltage limited to 5.2V
*
* Node Assignments
* noninverting input
* | inverting input
* | | Vs
* | | | ref
* | | | | enable
* | | | | | ground
* | | | | | | output
..SUBCKT AD8218 +IN -IN VS REF ENB GND OUT

*** Input Stage ***
EV 99 0 Value={ IF( V(VS) <4, V(+IN) , IF( V(VS) > 5.5, V(+IN), V(VS) )) }
Q1 3 1 7. 0 NPN
Q2 4 2 8 0 NPN
R1 99 3 1129
R2 99 4 1129
R3 7. 9 1e3
R4 8 9 1e3
I1 9 GND 400E-6
Ibp +IN GND 124E-6
Ibn -IN GND 124E-6

*** Input and Feedback Resistors ***
EOS 5 1 poly(1) (201,GND) 0 -1
R9 5 +IN 75e3
R10 REF 5 1.5e6
R11 -IN 2 75.045e3
R12 20 2 1.5e6

*** 1st Stage ***
D1 100 6 DZENER2
G1 100 10 1 2 .001
D2 10 6 DZENER1
R8 10 100 200e3

*** 2nd Stage ***
G2 100 20 10 100 .005
R7 20 100 1E6
C1 20 100 11.68E-9

*** Internal Reference ***
E1 100 0 7 0 1
R5 99 7 100e3
R6 7 GND 100e3

**** zero-pole stage
*G4 100 30 20 100 .59e-6
G4 100 30 20 100 .588e-6
R14 30 35 1e6
R16 35 100 1.7e6
L1 30 35 .65

**** 1st pole stage
G3 100 40 30 100 1e-6
R13 40 100 1E6
C2 40 100 186e-15

**** 2nd pole stage
G5 100 45 40 100 1e-6
R15 45 100 1E6
C3 45 100 186e-15
*C3 45 100 1e-15

*** Spectral Noise ***
VN GND 190 .65
DN 190 200 DNOISE
RN 200 GND 1
VM GND 200 0
FN GND 201 VM 1
RZ 201 GND 1

*** CMRR ***
*GCMR 500 0 505 0 .3e-9
*RCMR 500 501 1e6
*LCMR 501 0 80

GCMR 500 0 505 0 .3e-9
RCM1 500 501 549e6
LCMR 500 501 80
RCM2 501 0 1e6

GCM2 600 0 500 0 .85e-6
RCM3 600 0 1e6
CCM2 600 0 655e-15

RCMR1 +IN 505 10e6
RCMR2 505 -IN 10e6

*** Clamp
*D3 11 20 Dlow
D3 11 20 D
V7 11 0 0
D4 20 12 D
V8 +IN 12 .722

*** Output Stage ***
EAVG AVG GND Value={ ((V(+IN) + V(-IN))*0.5 )}
E02 65 0 Value={ IF( V(AVG) > 80, 5.2 , IF( V(AVG) < 4.0, 0, V(45))) }
E03 70 0 Value={ IF( V(ENB) == 0, V(65) + V(600) + .08, IF( V(ENB) != 0, V(65) + V(600), V(65) + V(600) )) }
E04 75 0 Value={ IF( V(70) > 5.2, 5.2 , IF( V(70) < 5.2, V(70)-.00491, V(70) )) }


*** Output Resistance
*Rout 70 OUT 2
Rout 75 OUT 2
*** Output Current limiting
Et 71 0 70 OUT 20
Qc 45 71 72 0 NPN
Re 72 0 10

..model D D
*.model Dlow D(Rdon=0 Rdoff=1e6 Vfwd=0.7)
*.model Dlow D(Ron=0 Roff=1e6 Vf=0.7)
..MODEL DZENER1 D(BV=2V, IS=1E-14, IBV=1E-3)
..MODEL DZENER2 D(BV=2V, IS=1E-14, IBV=1E-3)
..MODEL DNOISE D(AF=0, KF=0.0195e-10.5)
..model DILIM D(IS=1E-15)
..model NPN NPN

..end

 

[Fred Abse]

My first cut at it... with no part in hand, and one of the most useless
data sheets I've seen in years...

From: Jim Thompson <[email protected]>
Newsgroups: alt.binaries.schematics.electronic Subject: AD8218 Subcircuit
- AD8218_JT.lib Date: Sun, 18 Aug 2013 14:30:26 -0700 Message-ID:
<[email protected]>

If there's further interest I'll get a part, take some measurements myself
and refine all the details.

(My lab is currently boxed up while the new house is being built. When
it's finished I'll have a complete shop ;-)

This is just a self-amusement to demonstrate that I can write better
models than those... >:-}

Please report any bugs or incongruities with your brand of Spice
simulator.

A quick play with LTspice shows it works. I've not dug deep, yet, but, at
least the offset pin works like it should (and didn't with AD's model).

More later, when I've had a proper look.

 

[Fred Abse]

Great! My plan, at retirement, has been to do both, write a book and
make a business out of developing Spice models.

Now that ADI has provided a correction I'll A-B test mine against
theirs. My main guessing points were input bias current and what
floated nodes looked like. (I suspect they didn't address that
properly ;-)

No, they didn't. I had to add a couple of 1T resistors to their subckt, to
allow floating VS and ENB, to clear Spice warnings..

Your model shows more overshoot, and ringing, on 10mV pulse input, than
the ADI model.

I don't think much of the pulse generator it seems they used to measure
rise time (datasheet fig.11, green trace). >100ns rise? Yecch!

 

[Fred Abse]

I received the new AD8218.cir file. I haven't tried it yet. It should be
on the ADI website within the next week or so.

Better than the previous one.


Needs ".ends", not ".end"

Add to input stage:

*Allow VS and ENB to be floated
Rvsfloat VS GND 1T
Renbfloat ENB GND 1T

Gain error versus tempearture is stairstepped.

 

[Fred Abse]

On Fri, 23 Aug 2013 12:44:21 -0700, Fred Abse


I don't know. In a buck switcher, for example, the current isn't going to
change rapidly.

Yeah true, but for laboratory characterization?

I don't think I I've ever had a pulse generator that bad ;-)

 

[Fred Abse]

Change my OpAmp subcircuit params call to...

PARAMS: GBW=0.2 PM=60

Then it'll match the ADI model, but not the ADI data sheet >:-}

Doesn't change much, AFAICS.

Comparison posted to a.b.s.e.