We are always dealing with non-exact models, hence the calculations, for the non-exact model,
can meet all our rules on Thevenin's rules for analyzing circuits, but the model being inexact gives
us approximations. Much of the time we can use the approximations and move on, but there are
times in design where we use testing and characterization procedures to "finalize" the design. So
in your prior calculations you clearly notice nothing is present on PCB layout right ? But those traces,
their width, length, dielectric material, ground plane .....in some designs, especially RF type designs,
are used in modeling.
Now for this design you can generate ringing when working with MOSFETs in their gate circuit due
to a number of factors. So nominally you do the calc, fire up the design and examine the gate with
a fast scope to see if the gate node at device is ringing, if it is the R is too low a value to dampen the
Q, the L effects, in the drive path. But as we raise that R to do so, if needed, we start affecting rise
and fall times and hence power in the MOSFET, tradeoffs, always tradeoffs.
I am not trying to overwhelm you, just trying to fill in the edges of what one can experience when working
with MOSFETs and their non ideal behavior. Like Miller C effects as well.
As an aside good scope probing practices important :
https://www.testequity.com/UserFiles/documents/pdfs/tektronix/probe_fundamentals.pdf