Lack of bit field instructions in x86 instruction set because of patents ?

[Skybuck Flying]

Hello,

I have a question for you:

Can the lack of bit field instructions in the x86 instruction set be
explained by patents held by other cpu designers like motorola ?

Or is there another reason why x86 instruction set is missing bit field
instructions ?

Bye,
Skybuck.

 

[Glen Herrmannsfeldt]

Can the lack of bit field instructions in the x86 instruction set be
explained by patents held by other cpu designers like motorola ?

Or is there another reason why x86 instruction set is missing bit field
instructions ?

The 8008 didn't have them.

The 8080 was designed as an extended 8008.
The 8086 was the 8080 extended to 16 bits.

Also, you can do bit operations with AND and OR instructions.

-- glen

 

[Skybuck Flying]

What kind of bit field instruction(s) is lacking?

See motorola processor or nec processor.

InsertBits, ExtractBits, stuff like that

Bye,
Skybuck.

 

[Skybuck Flying]

The 8008 didn't have them.

The 8080 was designed as an extended 8008.
The 8086 was the 8080 extended to 16 bits.

Also, you can do bit operations with AND and OR instructions.

Yes but only one 8, 16, 32 bits all at once at fixed positions.

To manipulate only a few of those bits requires using masks, shifting,
and-ing, not-ing, or-ing, xor-ing etc.

Which can become quite a lot of instructions to do something "relatively
simply" like "insert" a few bits into some memory bit location.

(I wouldn't call it insert though... just "move/copy bits into a memory bit
location/offset".

A single clock/cycle instruction would be nice.... (or 1 latency in current
terms )

Bye,
Skybuck.

 

[Harold Aptroot]

Hello,

I have a question for you:

Can the lack of bit field instructions in the x86 instruction set be
explained by patents held by other cpu designers like motorola ?

Or is there another reason why x86 instruction set is missing bit field
instructions ?

Bye,
Skybuck.

So that means that BT, BTC, BTR and BTS were not sufficient? Your bitfields
must be larger?

 

[Ken Hagan]

Can the lack of bit field instructions in the x86 instruction set be
explained by patents held by other cpu designers like motorola ?

Certainly not, since bit-fields are both obvious and have been implemented
in a variety of machines for the past 50 years or so.

Or is there another reason why x86 instruction set is missing bit field
instructions ?

They aren't worth it. On the few occasions when you need the facility, a
mask and shift takes just two more instructions. (For comparisons or
arithmetic on similar bit-fields, you can even omit the shift step.)

 

[Alexei A. Frounze]

Yes but only one 8, 16, 32 bits all at once at fixed positions.

To manipulate only a few of those bits requires using masks, shifting,
and-ing, not-ing, or-ing, xor-ing etc.

Which can become quite a lot of instructions to do something "relatively
simply" like "insert" a few bits into some memory bit location.

(I wouldn't call it insert though... just "move/copy bits into a memory bit
location/offset".

A single clock/cycle instruction would be nice.... (or 1 latency in current
terms )

Bye,
  Skybuck.

Rotate through carry may be used to insert and delete single bits. If
you need many, then you either loop or use masks and all. SHLD/SHRD
may be helpful too, btw.

I think the reason why you don't see such advanced instructions on old
or primitive processors is because they're old and primitive. You
should feel lucky to have (I)MUL and (I)DIV. When I began to
program in ASM on Z80 (enhanced i8080) I didn't have this luxury.
Also, the CPU ran at only about 3 MHz and instructions took several
clocks. So, shifts, adds, LUTs -- all came handy.

Alex

 

[MooseFET]

The 8008 didn't have them.

The 8080 was designed as an extended 8008.
The 8086 was the 8080 extended to 16 bits.

If it really was the 8080 extended to more bits it would have been a
better processor. You would have been able to address 32 bits with
two 16 bit registers and not have to wait for a trip through the ALU
on every memory operation.

Also, you can do bit operations with AND and OR instructions.

The 8086 also had the "test" instruction to do an AND but not store
the results

 

[[email protected]]

See motorola processor or nec processor.

InsertBits, ExtractBits, stuff like that

Bye,
  Skybuck.

Could you please explain why, in your opinion, instructions such as
the following 8 bit instructions as well as the respective 16 and 32
bit do not fit the bill?


OR AL,bbbbbbbbB
AND AL,bbbbbbbbB
XOR AL,bbbbbbbbB
TEST AL,bbbbbbbbB

where "b" represents a zero or one bit.

 

[Jacko]

Hi

I think the reason why you don't see such advanced instructions on old
or primitive processors is because they're old and primitive. You
should feel lucky to have (I)MUL and (I)DIV. When I began to
program in ASM on Z80 (enhanced i8080) I didn't have this luxury.
Also, the CPU ran at only about 3 MHz and instructions took several
clocks. So, shifts, adds, LUTs -- all came handy.

Z80B, what a large chip, you lucky, lucky man. 6502 or even
http://nibz.googlecode.com

cheers jacko

 

[krw]

Because the 4004 didn't have them.

x86 is an entirely brain-damaged architecture. It's a good thing that
Intel has superb process technology and zero business ethics,
otherwise x86 would be a long-forgotten joke.

If IBM hadn't selected the 8088 for the original IBMPC (and then
bailed their asses out of a huge financial hole), Intel wouldn't
have had time to perfect its zero business ethics.

 

[MitchAlsup]

Can the lack of bit field instructions in the x86 instruction set be
explained by patents held by other cpu designers like motorola ?
No

Or is there another reason why x86 instruction set is missing bit field
instructions ?

Barcelona (AMD) introduced 5 (or was it 7) bit manipulation
instructions.

Mitch

 

[krw]

Yeah, tragic mistakes, selecting Intel and Microsoft. It could have
been Motorola and DR.

Wouldn't have been Motorola, but ignoring DR was an oversight.

 

[Skybuck Flying]

Here is an example of what a motorola processor presumeably does with one
instruction:

function KeepLowBits( Value : longword; Bits : longword ) : longword;
inline;
begin
Result := Value; // 32 bits case.
if Bits <= 31 then
begin
Result := Result and not (4294967295 shl Bits); // shl instruction limited
to 31.
end;
end;

function ShiftLeft( Left : longword; Right : Longword; Shift : longword ) :
longword;
asm
shld eax, edx, cl
end;

procedure WriteLongwordBits( Value : longword; Bits : longword; DestAddress
: pointer; DestBitIndex : longword );
var
vContent : longword;
vMask : longword;
vShift : longword;

vFirstContent : longword;
vSecondContent : longword;

vFirstMask : longword;
vSecondMask : longword;

vFirstAddress : longword;
vSecondAddress : longword;
begin
vContent := KeepLowBits( Value, Bits );
vMask := KeepLowBits( 4294967295, Bits );

vShift := DestBitIndex and 7;

vFirstContent := ShiftLeft( vContent, 0, vShift );
vSecondContent := ShiftLeft( 0, vContent, vShift );

vFirstMask := ShiftLeft( vMask, 0, vShift );
vSecondMask := ShiftLeft( 0, vMask, vShift );

vFirstAddress := longword(DestAddress) + (DestBitIndex shr 3); // div 32
vSecondAddress := vFirstAddress + 4;

Plongword(vFirstAddress)^ := (Plongword(vFirstAddress)^ and not vFirstMask)
or vFirstContent;
Plongword(vSecondAddress)^ := (Plongword(vSecondAddress)^ and not
vSecondMask) or vSecondContent;
end;

Bye,
Skybuck.

 

[Skybuck Flying]

Can the lack of bit field instructions in the x86 instruction set be

Certainly not, since bit-fields are both obvious and have been implemented
in a variety of machines for the past 50 years or so.

That doesn't stop people from filing patents on bit field instructions.

Maybe intel/amd is scared of law suits ?

They aren't worth it. On the few occasions when you need the facility, a
mask and shift takes just two more instructions. (For comparisons or
arithmetic on similar bit-fields, you can even omit the shift step.)

This will work up to a certain point... mostly when it's possible to
shift-or bits into single memory cell or registers.

As soon as multiple memory cells have to be overwritten things can get quite
nasty... especially if bits need to be preserved...

So I don't agree with you.

A simple example where "extract bits" instruction could be usefull is for
huffman decompression... where huffman codes can have a number of variable
bit fields stuck next to each other.

Extracting those bit fields (huffman codes) requires multiple x86
instructions, which slows down the huffman decoder.

A single instruction to do that would be preferred and would
probably/possibly give higher decoding speed and this is just one but an
important example !

Bye,
Skybuck =D

 

[[email protected]]

Barcelona (AMD) introduced 5 (or was it 7) bit manipulation
instructions.

And the original (A stepping) '386 had Insert Bits and Extract Bits
instructions. Apparently Intel needed the microcode space, and pulled
them in the B steppings.

 

[Alexei A. Frounze]

Hi


Z80B, what a large chip, you lucky, lucky man. 6502 or evenhttp://nibz.googlecode.com

cheers jacko

I programmed the tiny i8051 as well. Even though it does have MUL, DIV
and even bit addressing of the RAM's bytes (btw, just 128 bytes of
internal RAM for stack and variables -- how cool is that?, it's far
more inferior than Z80.

Alex

 

[MitchAlsup]

So that means that BT, BTC, BTR and BTS were not sufficient? Your bitfields
must be larger?

Single bit "fields" are totally inadequate, and the x86 instructions
rather more so.

Mitch

 

[H. Peter Anvin]

Single bit "fields" are totally inadequate, and the x86 instructions
rather more so.

Totally inadequate *FOR WHAT*? Why are the instructions you propose
better than shift and mask?

-hpa

 

[FunkyPunk FieldEffectTrollsistor]

Single bit "fields" are totally inadequate, and the x86 instructions
rather more so.

Mitch

Simple answer:

One is CISC, and the other is RISC.