Lack of bit field instructions in x86 instruction set because of patents ?

[Vladimir Vassilevsky]

Lets inject some facts into this thread; after that y'all can return to
the usual mix of information, mis-information, talking past each other
and name-calling.

Finally I met the professor who designs superscalar MIPS cores. One of
his previous works was about identifying the hot spots in the CPU. This
is what he told me:

1. Caches are definitely the coolest areas of the CPU; one can clearly
see that on the IR pictures. It is hard to tell about the other parts;
it depends; especially as the modern CPUs turn off the areas which are
not in use.

2. Pure asynchronous logic is not used. However there are some logic
blocks where the result of the operation is latched on the second clock;
those blocks are used in multipliers, dividers and like. It seems like
nobody got anything practical from the async logic with the processing
delay of more then two clocks.

3. Static vs dynamic power consumption - it depends. On the sub-volt
high speed logic, static and dynamic losses are comparable.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

 

[krw]

Finally I met the professor who designs superscalar MIPS cores. One of
his previous works was about identifying the hot spots in the CPU. This
is what he told me:

So? Second hand knowledge, at best, passed down to someone who doesn't
understand.

1. Caches are definitely the coolest areas of the CPU; one can clearly
see that on the IR pictures.

Of *course* they are. Every FF in a processor is clocked every cycle.
Only the cache line being accessed is active. Of course it's going to
be cooler. The only power dissipation in the inactive cells is caused
by leakage (which is not insignificant but obviously less than the
active power).

It is hard to tell about the other parts;
it depends; especially as the modern CPUs turn off the areas which are
not in use.

Baloney. They are clock gated, they are *not* "turned off", unless
the entire pipeline is dormant for some time. Entire CPUs are powered
off when not in use.

2. Pure asynchronous logic is not used. However there are some logic
blocks where the result of the operation is latched on the second clock;
those blocks are used in multipliers, dividers and like. It seems like
nobody got anything practical from the async logic with the processing
delay of more then two clocks.

Define "asynchronous logic". Domino logic certainly is used. The
rest of this is BS.

3. Static vs dynamic power consumption - it depends. On the sub-volt
high speed logic, static and dynamic losses are comparable.

Absolute nonsense.

 

[H. Peter Anvin]

In one case I recall using the CGA display *as* the debugger.>

I did that yesterday. (OK, so it was a mega-hyper-super-VGA card, but
running in plain old CGA mode.)

-hpa