This circuit drags the voltage to it's one stabile state. Whenever you have a logic circuit, it always helps to decide what the initial state will be. In other words what is the startup condition and will it change. There exists a voltage that the circuit likes best, that is the stabile state voltage. When the capacitors are all charged to whatever voltage they can take on, you have arrived at it's stabile state. Now what about the oscillator. The oscillator has no stabile state because it's logic is in direct defiance and rely's on the capacitor's arrival to the correct voltage which is always going to be alternately high and low. The reason for this lies in the arrangement of the gates. Oscillators have a gate arrangement that says the logic does not produce a steady state. Like an inverter fed back onto itself with a capacitor that will charge to it's next stabile state which will in turn lead to it's next stabile state. If you think about it, the time should be very short depending on the RC. But considering it's linearity, the time should indeed be short with only the voltage having to drop or rise by mere millivolts, but for only the 1.7 volt unknown zone of the logic which leads to slew.