LTspice subckt model for AD734

[JosephKK]

I picked up the macromodel from AD(TI) for this IC. I
am using the manual to try to figure out how to
incorporate the model in a circuit idea, but i hit up
against errors. This one has me baffled though.

The error i am getting is:

"Port(pin) count mismatch between the definition of 'ad734.cir' and instance xu1. The instance has more connections than the definition."

I don't understand why i am getting this error.
I would like to better understand how to make this work.


Here is example test circuit:

+++++
Version 4
SHEET 1 2476 680
WIRE 800 -1120 688 -1120
WIRE 688 -1088 688 -1120
WIRE 800 -1088 800 -1120
WIRE 208 -1008 112 -1008
WIRE 0 -992 0 -1040
WIRE 208 -992 208 -1008
WIRE 640 -896 448 -896
WIRE 800 -896 800 -1008
WIRE 800 -896 640 -896
WIRE 208 -864 208 -912
WIRE 320 -864 320 -1040
WIRE 320 -864 208 -864
WIRE 0 -848 0 -912
WIRE 112 -848 112 -1008
WIRE 112 -848 0 -848
WIRE 0 -816 0 -848
WIRE 448 -608 448 -896
WIRE 496 -608 448 -608
WIRE 704 -608 704 -656
WIRE 704 -608 640 -608
WIRE 496 -576 464 -576
WIRE 656 -576 640 -576
WIRE 464 -544 464 -576
WIRE 464 -544 432 -544
WIRE 496 -544 464 -544
WIRE 672 -544 640 -544
WIRE 672 -528 672 -544
WIRE 816 -528 672 -528
WIRE 432 -512 432 -544
WIRE 464 -512 464 -544
WIRE 496 -512 464 -512
WIRE 672 -512 672 -528
WIRE 672 -512 640 -512
WIRE 464 -480 464 -512
WIRE 496 -480 464 -480
WIRE 768 -480 768 -608
WIRE 768 -480 640 -480
WIRE 192 -448 192 -480
WIRE 192 -448 48 -448
WIRE 496 -448 192 -448
WIRE 656 -448 640 -448
WIRE 464 -416 464 -480
WIRE 496 -416 464 -416
WIRE 672 -416 640 -416
WIRE 672 -304 672 -416
WIRE 704 -304 704 -320
WIRE 704 -304 672 -304
WIRE 768 -304 768 -480
WIRE 768 -256 768 -304
WIRE 48 208 48 -448
WIRE 48 368 48 288
FLAG 48 368 0
FLAG 688 -1088 0
FLAG 0 -1040 VP
FLAG 320 -1040 VN
FLAG 0 -816 0
FLAG 704 -656 VP
FLAG 704 -320 VN
FLAG 768 -256 0
FLAG 432 -512 0
FLAG 192 -480 Ain
FLAG 640 -896 C0
SYMBOL voltage 48 192 R0
WINDOW 3 46 82 Left 0
WINDOW 123 46 50 Left 0
WINDOW 39 47 110 Left 0
SYMATTR Value SINE(0 1 220 0 0 0)
SYMATTR Value2 AC 1 0
SYMATTR SpiceLine Rser=1 Cpar=100p
SYMATTR InstName V1
SYMBOL voltage 800 -1104 R0
WINDOW 3 43 69 Left 0
WINDOW 123 43 41 Left 0
WINDOW 39 44 95 Left 0
SYMATTR Value SINE(0 1 10.7M 0 0 0)
SYMATTR Value2 AC 1 0
SYMATTR SpiceLine Rser=5 Cpar=1p
SYMATTR InstName V5
SYMBOL voltage 0 -1008 R0
SYMATTR InstName V7
SYMBOL voltage 208 -1008 R0
SYMATTR InstName V8
SYMBOL AD734 576 -560 R0
SYMATTR InstName U1
SYMATTR Prefix X1 X2 U0 U1 U2 Y1 Y2 VN ER Z2 Z1 W DD VP
SYMATTR SpiceModel ad734.cir
SYMBOL cap 704 -592 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL cap 704 -288 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C3
SYMATTR Value 100n
TEXT 48 -1088 Left 0 !.subckt ad734.cir
TEXT -32 392 Left 0 !.tran 10m

=====


Here is the downloaded macromodel:

+++++
* AD734 SPICE Macro-model 4/92, Rev. B
* AAG / PMI
*
* Revision History:
* Removed input signal current compensation: GX1,GY1,GZ1
* Added Isy vs. Vsy
*
* Copyright 1992 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* X1
* | X2
* | | UO
* | | | U1
* | | | | U2
* | | | | | Y1
* | | | | | | Y2
* | | | | | | | VN
* | | | | | | | | ER
* | | | | | | | | | Z2
* | | | | | | | | | | Z1
* | | | | | | | | | | | W
* | | | | | | | | | | | | DD
* | | | | | | | | | | | | | VP
* | | | | | | | | | | | | | |
..SUBCKT AD734 10 11 49 50 51 20 21 200 58 31 30 77 54 100
*
EREF 300 0 POLY(2) 100 0 200 0 (0,0.5,0.5)
*
* X INPUT STAGE & POLE AT 40 MHz
*
CINX 10 11 2E-12
IBX1 10 0 DC 50E-9
IBX2 11 0 DC 50E-9
EOSX 12 10 POLY(1) 18 300 15E-3 1
RX1 12 13 25E3
RX2 13 11 25E3
*
GX1 300 14 12 11 1E-6
RX3 14 300 9.995E5
CX1 14 300 3.9809E-15
VX1 100 15 DC 3.1875
DX1 14 15 DX
VX2 16 200 DC 3.1875
DX2 16 14 DX
*
* X INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
*
ECMX 17 300 13 300 56.234
RCMX1 17 18 1E6
CCMX 17 18 3.9789E-12
RCMX2 18 300 1
*
* Y INPUT STAGE & POLE AT 40 MHz
*
CINY 20 21 2E-12
IBY1 20 0 DC 50E-9
IBY2 21 0 DC 50E-9
EOSY 22 20 POLY(1) 28 300 10E-3 1
RY1 22 23 25E3
RY2 23 21 25E3
*
GY1 300 24 22 21 1E-6
RY3 24 300 9.995E5
CY1 24 300 3.9809E-15
VY1 100 25 DC 3.1875
DY1 24 25 DX
VY2 26 200 DC 3.1875
DY2 26 24 DX
*
* Y INPUT STAGE COMMON-MODE REJECTION AND ZERO 80 kHz
*
ECMY 27 300 23 300 56.234
RCMY1 27 28 1E6
CCMY 27 28 1.9895E-12
RCMY2 28 300 1
*
* Z INPUT STAGE & POLE AT 40 MHz
*
CINZ 30 31 2E-12
IBZ1 30 0 DC 50E-9
IBZ2 31 0 DC 50E-9
EOSZ 32 30 POLY(1) 38 300 20E-3 1
RZ1 32 33 25E3
RZ2 33 31 25E3
*
GZ1 300 34 32 31 1E-6
RZ3 34 300 1E6
CZ1 34 300 3.9789E-15
VZ1 100 35 DC 3.1875
DZ1 34 35 DX
VZ2 36 200 DC 3.1875
DZ2 36 34 DX
*
* Z INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
*
ECMZ 37 300 33 300 56.234
RCMZ1 37 38 1E6
CCMZ 37 38 3.9789E-12
RCMZ2 38 300 1
*
* DENOMINATOR CONTROL & INTERNAL REFERENCE
*
QU1 100 49 50 QNU
RU1 50 51 28E3
*
VU 100 52
QU2 52 0 53 QNU
RU2 53 54 0.001
IU 53 200 DC 10E-6
FU1 300 55 VU 1.01
RU3 55 300 1E6
*
VR1 57 200 DC 8
QR 59 57 58 QPU
RR 57 58 1E5
VR2 59 200
FU4 300 56 VR2 1
RU4 56 300 28E3
*
EU 60 300 POLY(3) 50 51 55 300 56 300 (0,1.0101,1,1.0101)
RU5 60 300 1E6
*
* 250 MHz MULTIPLIER CORE
*
EXY 46 300 POLY(2) 14 300 24 300 (0,0,0,0,1)
RXY 46 300 1E6
GXY 300 47 46 300 1
GU 47 300 POLY(2) 60 300 47 300 (0,0,0,0,1)
RU 47 300 1E12
CU 47 300 6.65E-9
EW 48 300 POLY(2) 47 300 34 300 (0,1,-1)
RW 48 300 1E6
*
* OUTPUT AMP BUFFER
*
GW 64 300 48 300 1
QW1 100 0 61 QNW
QW2 200 0 62 QPW
QW3 63 62 64 QNW
QW4 65 61 64 QPW
RW1 100 63 1
RW2 65 200 1
IW1 100 62 DC 100E-6
IW2 61 200 DC 100E-6
VW1 100 66 DC 10
DW1 66 63 DX
VW2 67 200 DC 10
DW2 65 67 DX
*
* OUTPUT AMP GAIN STAGE
*
GW1 300 68 100 63 1
GW2 68 300 65 200 1
RW3 68 300 1.38E3
CW1 68 300 19E-9
VW3 100 69 DC 3.8
DW3 68 69 DX
VW4 70 200 DC 3.8
DW4 70 68 DX
*
* TRANSIENT SUPPLY CURRENT COMPENSATION
*
DCC1 80 100 DX
GCC 0 80 48 300 1
DCC2 0 80 DX
DEE1 81 0 DX
GEE 81 0 300 48 1
DEE2 200 81 DX
*
* POLE AT 17.5 MHz
*
GW3 300 71 68 300 1E-6
RW4 71 300 1E6
CW2 71 300 9.0946E-15
*
IDC 100 200 DC 4.0125E-3
RDC1 100 78 3.2E3
RDC2 78 200 3.2E3
DO1 100 72 DX
GO1 72 200 76 71 25E-3
DO2 200 72 DY
DO3 100 73 DX
GO2 73 200 71 76 25E-3
DO4 200 73 DY
VSC1 74 76 DC 0.4
DSC1 71 74 DX
VSC2 76 75 DC 0.4
DSC2 75 71 DX
GO3 76 100 100 71 25E-3
GO4 200 76 71 200 25E-3
RO1 100 76 40
RO2 76 200 40
LO 76 77 100E-9
*
* MODELS USED
*
..MODEL QNU NPN (BF=100 IS=1E-16)
..MODEL QPU PNP (BF=100 IS=1E-16)
..MODEL QNW NPN (BF=1E9 IS=1E-15)
..MODEL QPW PNP (BF=1E9 IS=1E-15)
..MODEL DX D(IS=1E-15)
..MODEL DY D(IS=1E-15 BV=50)
..ENDS AD734

=====

Here is the symbol i created:

+++++
Version 4
SymbolType CELL
RECTANGLE Normal 64 187 -80 -85
TEXT -58 -106 Left 0 AD734
SYMATTR ModelFile AD734.cir
SYMATTR Prefix U
SYMATTR SpiceModel AD734
PIN -80 -48 LEFT 8
PINATTR PinName X1
PINATTR SpiceOrder 1
PIN -80 -16 LEFT 8
PINATTR PinName X2
PINATTR SpiceOrder 2
PIN -80 16 LEFT 8
PINATTR PinName U0
PINATTR SpiceOrder 3
PIN -80 48 LEFT 8
PINATTR PinName U1
PINATTR SpiceOrder 4
PIN -80 80 LEFT 8
PINATTR PinName U2
PINATTR SpiceOrder 5
PIN -80 112 LEFT 8
PINATTR PinName Y1
PINATTR SpiceOrder 6
PIN -80 144 LEFT 8
PINATTR PinName Y2
PINATTR SpiceOrder 7
PIN 64 144 RIGHT 8
PINATTR PinName VN
PINATTR SpiceOrder 8
PIN 64 112 RIGHT 8
PINATTR PinName ER
PINATTR SpiceOrder 9
PIN 64 80 RIGHT 8
PINATTR PinName Z2
PINATTR SpiceOrder 10
PIN 64 48 RIGHT 8
PINATTR PinName Z1
PINATTR SpiceOrder 11
PIN 64 16 RIGHT 8
PINATTR PinName W
PINATTR SpiceOrder 12
PIN 64 -16 RIGHT 8
PINATTR PinName DD
PINATTR SpiceOrder 13
PIN 64 -48 RIGHT 8
PINATTR PinName VP
PINATTR SpiceOrder 14

=====

 

[Helmut Sennewald]

----- Original Message -----

From: "JosephKK" <[email protected]>
Newsgroups: sci.electronics.design
Sent: Sunday, April 04, 2010 3:37 AM
Subject: LTspice subckt model for AD734
I picked up the macromodel from AD(TI) for this IC. I
am using the manual to try to figure out how to
incorporate the model in a circuit idea, but i hit up
against errors. This one has me baffled though.
The error i am getting is:
"Port(pin) count mismatch between the definition of 'ad734.cir' and
instance xu1.
The instance has more connections than the definition."
I don't understand why i am getting this error.
I would like to better understand how to make this work.

Hello Joseph,

1. The Prefix in the symbol has to be always X for subcircuits.
Don't forget to re-instantiate the symbol in the schematic after this
change.

2. Delete this SPICE-directive ".subckt..." in your schematic.

3. The value of the voltage sources should be 15.

4. The multiplier M or m means milli. Maybe you want MEG or meg.

5. After you have fixed this, you may encounter problems with convergence.
You have to add the following SPICE-directives to get it working.

..options tseed=1n
..options method=gear
..options cshunt=7e-15

Unfortunately the ladder has already some impact on the bandwidth
of the AD737 at 10MHz.

If you just need a multiplier for some kind of higher level simulation,
then better use the behavioral sources Bv or Bi.
A multiplier:
V=V(nodea)*V(nodeb)

You should consider to become a member of the LTspice group.
An example with the AD734 has been already there in the group's
Files-section. Files > Lib > AD734
http://tech.groups.yahoo.com/group/LTspice/
To become a member is very easy if you create an email-account
in Yahoo before.

Best regards,
Helmut

 

[JosephKK]

Hello Joseph,

1. The Prefix in the symbol has to be always X for subcircuits.
Don't forget to re-instantiate the symbol in the schematic after this
change.

reinstantiating was easy enough

2. Delete this SPICE-directive ".subckt..." in your schematic.
ok.

3. The value of the voltage sources should be 15.
Fixed

4. The multiplier M or m means milli. Maybe you want MEG or meg.
Changed

5. After you have fixed this, you may encounter problems with convergence.
You have to add the following SPICE-directives to get it working.

After i get operating point to go. Floating nodes.

.options tseed=1n
.options method=gear
.options cshunt=7e-15

Unfortunately the ladder has already some impact on the bandwidth
of the AD737 at 10MHz.

Mostly an output amplifier slew rate limitation. I can dodge that well enough.

If you just need a multiplier for some kind of higher level simulation,
then better use the behavioral sources Bv or Bi.
A multiplier:
V=V(nodea)*V(nodeb)

I was trying to get a bit further away from that, but that is inside
the macromodel anyway. I intended to create a buildable circuit.

You should consider to become a member of the LTspice group.
An example with the AD734 has been already there in the group's
Files-section. Files > Lib > AD734
http://tech.groups.yahoo.com/group/LTspice/
To become a member is very easy if you create an email-account
in Yahoo before.

Sorry, they pissed me off. I couldn't read, search, or do anything
before signing up; i understand signing up to post though.
I have problems with managing all the damn passwords i use as is.
Not the way to attract friends.

 

[Fred Abse]

Sorry, they pissed me off. I couldn't read, search, or do anything
before signing up; i understand signing up to post though.
I have problems with managing all the damn passwords i use as is.
Not the way to attract friends.

Same here...

 

[JosephKK]

Poor babies

I subscribed to receive the digests, and often post answers from
there, without having to use the website.

...Jim Thompson

Understandable, i avoid blogs like the pox they are.

 

[Fred Abse]

The pin/node count matches. Comment out the "OPTIONAL:" line and see
what happens.

It appears that it is necessary to include the whole Orcad mix_misc
library, plus other libraries which mix_misc references.

I don't like libraries that require other libraries. Stinks of
programmers' methods. Change one thing and break lots of others.

Also, the Orcad libraries include syntax that LTSpice doesn't understand.

Major rewrite necessary.

 

[Fred Abse]

OrCAD (and PSpice, for that matter) can utilize global power and
ground nodes as a means to keeping schematics from becoming a jungle
of wires.

You _could_ learn to make your own libraries (I do ;-)

I already do. I don't have any use for a CD4046 model, I was just
investigating the OP's problem to see if I could offer anything
constructive.

PSpice models usually just work in LTSpice. Some of the Orcad stuff seems
a bit byzantine.

 

[Fred Abse]

I missed your next-to-last paragraph. With enough flattery I could
probably be cajoled into writing a CD4046 that's a generic
(behavioral) Spice model ;-)

That's what I'd do. I like behavioral models. However it isn't me that
wants one, it's volkerk. I don't know whether his flattery skills are
sufficiently honed ;-)

Byzantine: characterized by elaborate scheming and intrigue, esp. for the
gaining of political power or favor. (Dictionary.com)

 

[tm]

I missed your next-to-last paragraph. With enough flattery I could
probably be cajoled into writing a CD4046 that's a generic
(behavioral) Spice model ;-)

...Jim Thompson

Yer an ugly old coot and I don't think you can do it!


How's that for cajoling?

tm

PS, I like your sig.

 

[Fred Abse]

I'm not a programmer, but my understanding is that the PSpice digital
behavioral models are based on "C" code. Charlie?

Invented by Kernighan and Ritchie, as an elaborate practical joke

 

[Charlie E.]

I'm not a programmer, but my understanding is that the PSpice digital
behavioral models are based on "C" code. Charlie?

...Jim Thompson

Actually, it is probably more complicated than that, and simpler. I
know that the the time step processes gave them fits, especially for
fast transitions, but that when they were done they were pretty happy
about it. But, basically, they did actually digital logic, and then
wrapped an AtoD and DtoA around it. When they did PLSyn for
programmable logic, like Xilinx FPGAs, they used the logic expressions
provided for the PLA and the timing expressions, and then did the A-D
translations at the borders. The PSpiceHDL tool would have used
NC-SIM as the VHDL or Verilog simulator, with the same types of
translations, including IBIS models. However, that would have sold in
the $20K range, and been a valid replacement for $200K tools, so they
just eliminated the entire development team...

Charlie

 

[Helmut Sennewald]

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

 

[Helmut Sennewald]

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

[snip]

Hi Helmut,

Thanks for a clean hierarchical schematic!

Amusing myself with how to make a full behavioral model...

Do you have any ideas on how to characterize a CMOS inverter?

I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house

Hello Jim,

I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.

Best regards,
Helmut

 

[Joerg]

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

[snip]

Hi Helmut,

Thanks for a clean hierarchical schematic!

Amusing myself with how to make a full behavioral model...

Do you have any ideas on how to characterize a CMOS inverter?

I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house

Hello Jim,

I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.

Helmut, do you have any idea why the LTSpice group might "forget"
members? It shows up under "My Groups" but then a screen pops up to
"Join Now". Weird.

Any chance this group might be newsserver accessible some day? Most
technical ones already are, via gmane. The Yahoo interface is IMHO a
pain, inefficient and very slow.

 

[Joerg]

im Newsbeitrag On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

[snip]

Hi Helmut,

Thanks for a clean hierarchical schematic!

Amusing myself with how to make a full behavioral model...

Do you have any ideas on how to characterize a CMOS inverter?

I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house
Hello Jim,

I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.

Helmut, do you have any idea why the LTSpice group might "forget"
members? It shows up under "My Groups" but then a screen pops up to
"Join Now". Weird.

Any chance this group might be newsserver accessible some day? Most
technical ones already are, via gmane. The Yahoo interface is IMHO a
pain, inefficient and very slow.

Subscribe to the E-mailed "digests". I do. I go thru the Yahoo
interface so rarely I have trouble remembering my password ;-)

Can you post via that?

Of course I still predominately use PSpice, but the group is just
stock-full of great ideas, and pro-level posters... Helmut and
Woodgate... yep _our_ Woodgate.

Yes, that is very true. The icing on the cake would be if Mike
Engelhardt would stick his head in there once in a while.

 

[Joerg]

Helmut Sennewald wrote:
im Newsbeitrag On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

[snip]

Hi Helmut,

Thanks for a clean hierarchical schematic!

Amusing myself with how to make a full behavioral model...

Do you have any ideas on how to characterize a CMOS inverter?

I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house
Hello Jim,

I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.

Helmut, do you have any idea why the LTSpice group might "forget"
members? It shows up under "My Groups" but then a screen pops up to
"Join Now". Weird.

Any chance this group might be newsserver accessible some day? Most
technical ones already are, via gmane. The Yahoo interface is IMHO a
pain, inefficient and very slow.
Subscribe to the E-mailed "digests". I do. I go thru the Yahoo
interface so rarely I have trouble remembering my password ;-)

Can you post via that?

I think so. I've certainly "Replied to group" with suggestions of
solutions to problems.

That would be cool. But first I have to find out why it won't let me in
anymore, else I won't be able to set anything.

[...]

 

[Helmut Sennewald]

"Jim Thompson" <[email protected]>
schrieb
im Newsbeitrag news:[email protected]...

On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

[snip]

Hi Helmut,

Thanks for a clean hierarchical schematic!

Amusing myself with how to make a full behavioral model...

Do you have any ideas on how to characterize a CMOS inverter?

I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house

Hello Jim,

I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.

Helmut, do you have any idea why the LTSpice group might "forget"
members? It shows up under "My Groups" but then a screen pops up to
"Join Now". Weird.

Any chance this group might be newsserver accessible some day? Most
technical ones already are, via gmane. The Yahoo interface is IMHO a
pain, inefficient and very slow.

Hello Joerg,

"Join now" only menas you have to login with your password.
This happens after a every few weeks for safety reason.
Somebody from Yahoo had this bad idea to name this "Join now" instead of
"Login".

Type in your login and password.
In the next window, directly go to Messages.

Best regards,
Helmut

 

[Helmut Sennewald]

On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

[snip]

Hi Helmut,

Thanks for a clean hierarchical schematic!

Amusing myself with how to make a full behavioral model...

Do you have any ideas on how to characterize a CMOS inverter?

I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house

Hello Jim,

I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.

Best regards,
Helmut

Hi Helmut,

I wasn't thinking transistor-level, just a behavioral equivalent that
avoided special digital structures... make an inverter from G-sources
and a capacitor or two.

That led me to thinking that an NMOS device is just a two-variable
G-source (VGS and VDS) with a TANH equation...

Then one could make up their own accurate digital library using analog
behavioral components

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house

Hello Jim,

A simulation with digital devices is much faster than the same with analog
devices.

Best regards,
Helmut

 

[Joerg]

"Jim Thompson" <[email protected]>
schrieb
im Newsbeitrag On Sun, 10 Oct 2010 11:51:58 +0200, "Helmut Sennewald"

Hello,

I have written sometimes ago a CD4046 model for LTspice.
You can download it from the LTspice Yahoo group.

http://tech.groups.yahoo.com/group/LTspice/
Files > Lib > CD4046

Best regards,
Helmut

[snip]

Hi Helmut,

Thanks for a clean hierarchical schematic!

Amusing myself with how to make a full behavioral model...

Do you have any ideas on how to characterize a CMOS inverter?

I think you could characterize an inverter as an input capacitance
versus input voltage and the output as a resistance variable with
input voltage and also with a capacitance likewise related.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I can see November from my house
Hello Jim,

I haven't needed the CD4046 for myelf. I guess somebody
asked for it. My goal has been to use the highest possible
level of components to get it quickly done. Thus I tried
to avoid the transistor level as much as possible.

Helmut, do you have any idea why the LTSpice group might "forget"
members? It shows up under "My Groups" but then a screen pops up to
"Join Now". Weird.

Any chance this group might be newsserver accessible some day? Most
technical ones already are, via gmane. The Yahoo interface is IMHO a
pain, inefficient and very slow.

Hello Joerg,

"Join now" only menas you have to login with your password.
This happens after a every few weeks for safety reason.
Somebody from Yahoo had this bad idea to name this "Join now" instead of
"Login".

Type in your login and password.
In the next window, directly go to Messages.

Thanks, Helmut, but it doesn't work anymore. After entering name and
password a 2nd time it pops over to regular Yahoo. Wants all that a 3rd
time but won't take it. Plus it moans and groans about cookies before
that and then sets ad cookies.

IMHO they have royally screwed up this time. Can't you open the LTSpice
group to gmane like the other tech groups? Then all this script kiddie
nonsense is gone and people can use it like a real newsgroup. Without
the file section, of course, for that one would have to wade through the
morass (or try ...).

 

[Fred Abse]

That would be cool. But first I have to find out why it won't let me in
anymore, else I won't be able to set anything.

I've tried to register several times. Each time it's failed with various
messages about cookies (enabled) Javascript (enabled), or just plain not
responding. Eventually, I gave up. A plague on its house!

BTW have you noticed the fine print? "Yahoo collects personal data".