Win's next 10kV project, a 1us ramp

[Tony Williams]

http://www.picovolt.com/win/elec/ckts/spice/RIS-583/4kV-1A_FQD2N100.pdf

Fascinating stuff. OK, it is a simulation, but
apparent success is almost unbelievable.

What does the energy in each die look like, per pulse?

 

[Fred Bartoli]

Wear safety glasses.

But seriously, how about some diodes to clip the gate excursions? I
know, Spice says the voltages will track perfectly. IMHO asking for
2% tracking shows an awful lot of faith in the matching of dynamic
transconductances.

No need at all for transconductance matching. This is just a string of
cascoded cascodes.

Win,
I first thought that there could be some pb with mosfets' capacitance
mismatch, but there isn't: you start with high voltage, equally distributed
between all the MOSFETs (due to the 10M) which is then reduced by the
capacitive string, whatever the capacitance mismatch. Thus the voltage can
never exceed the peek voltage you choose and this relieve you from adding...
additional Fets.
It'd had been more painful had you wanted a positive ramp... (looking at the
datahseet)
Hmm, maybe even not since they are nicely avalanche rated. And their low Qgd
will help too.
So, resetting the output voltage will probably require no extra care.

My guess is that with such a low Qgd (6.5nC is 20V on 330p) that you can
probably lower the 330p, to maybe 100p, and reduce the capacitive string
"parasitic" current.

As for the ID falling at the end of pulse, it can only come from a
gate-source current but I think it's unlikely on a real fet: at 150V VDS
you're still well in the gate plateau and thus it can't be a CGS current.
Did you check your model on this point?

It's not clear to me where the ID prop delays and VGS prop delay/spike comes
from (not much time available) but I guess the Coss(s?) have something to do
there.

When I saw your first post about this "self dividing cascode" I thought yes,
that's the ticket. I still think it is. And pretty elegant too.

I started to build a spice sim, but the editor crashed before I had a chance
to save. Can you send me your file (I too run intusoft). That'll save some
of the time I'm short of ATM.

 

[Winfield Hill]

Fred Bartoli wrote...

My guess is that with such a low Qgd (6.5nC is 20V on 330p) that you can
probably lower the 330p, to maybe 100p, and reduce the capacitive string
"parasitic" current.

Yes, I thought of that, we'll see how it progresses.

As for the ID falling at the end of pulse, it can only come from a
gate-source current but I think it's unlikely on a real fet: at 150V VDS
you're still well in the gate plateau and thus it can't be a CGS current.
Did you check your model on this point?

It's a puzzle, I'm going to look again when I get to work.

It's not clear to me where the ID prop delays and VGS prop delay/spike
comes from (not much time available) but I guess the Coss(s?) have
something to do there.

The prop delay is easy to understand, consider the sinking current from
the source and assign it all to charging up Ciss, until the MOSFET gate
gets up to the right conduction region. That's why I pre-biased the
string at 0.3mA, to reduce the charging voltage, and the delay time.
One thing, the abnormally-high Vgs my modified FET model exhibits can
only further slow the modeled prop delay. So the real circuit may be
faster. But the factory's Rg value may be too low, and gate spreading
resistance may mean the real circuit will be slower... Funny thing,
spreading resistance. Some of the FET's gate structure is immediately
available, some is delayed a bit, and the rest is delayed a lot. So a
good high-speed model would divide the FET into paralleled sections,
each with its own spreading resistance values, from low to high.

When I saw your first post about this "self dividing cascode" I thought
yes, that's the ticket. I still think it is. And pretty elegant too.

I started to build a spice sim, but the editor crashed before I had a
chance to save. Can you send me your file (I too run intusoft). That'll
save some of the time I'm short of ATM.

OK, I've posted the files to my website. Have fun.
http://www.picovolt.com/win/elec/ckts/spice/RIS-583/

 

[Winfield Hill]

Ancient_Hacker wrote...

Wear safety glasses.

But seriously, how about some diodes to clip the gate excursions?
I know, Spice says the voltages will track perfectly. ...

Any real circuit I make will have the diodes. But for some reason
I've had difficulty getting Spice to converge with lots of cascode
MOSFETs and with gate-source zener diodes. I have to isolate the
zeners with series resistors to the point they don't contribute to
the performance, so I've learned to leave them out from the start.
The zener's capacitance is under ~ 20% of the MOSFET's Ciss anyway.
Yes, I know that's another error.

 

[Winfield Hill]

Tony Williams wrote...

http://www.picovolt.com/win/elec/ckts/spice/RIS-583/4kV-1A_FQD2N100.pdf

Fascinating stuff. OK, it is a simulation, but
apparent success is almost unbelievable.

Yeah, but unbelievable can cut both ways, check the results with
the unmodified Fairchild model for unbelievable!

What does the energy in each die look like, per pulse?

Good question. The power starts out at about 1kW, has a short
10ns peak to 1.3kW and ramps down. According to spice, that's
a minuscule 211uJ during the 450ns duration I have in this test.

The FQD2N100 datasheet says its rated at 160mJ for the test pulse,
"L = 120mH, IAS = 1.6A, VDD = 50V, RG = 25, Starting TJ = 25°C"
which works out to, let's see, Bvdss-Vdd is say 1150V, so we get
dI/dt = 1150/0.12 = 9583A/s, or 167us long. Scaling this to the
1us pulse I'm aiming at, using the square-root rule, I'm allowed
160/sqrt 167 = 12.4mJ. So our 0.21mJ is truly minuscule.