3 stage timer design

[cliffclavin]

Hello

I have some experience building electronic kits as a kid - radio's, transmitters, amp's etc. Later at University I was taught aspects of digital design using Electronics workbench - such as logic gates, flip flops, binary adders etc

I have a basic working knowledge but with some gaps. My main problem is I do not have electronics workbench or university lecturers handy to help...

I am trying to build a simple timer that cycles between 3 set delays, while energising two relays. One relay is on during the first time period, and the other relay is on during the last time period.

My idea is to use both sides of a D Type Flip Flop - and use the 2 flip flops to cycle between the three time periods. And use three 4017 Decade counters, and a 555 astable for clock pulses.

A capacitor & some diodes will 'set' both flip flops in the approprate mode on power-up so they are in sync. This is not shown on the diagram.

My idea:

Counter A starts count. Relay B is on

Counter A finishes count, resets flip flop A, Relay B is off. Starting Counter B.

Counter B finishes count, Resets flip flop B, Starting Counter C, Relay A turns on.

Counter C finished count, Sets Flip Flops A and B, Relay A turns off. Relay B Turns ON, Counter A starts count.

I have drawn a diagram of how I think this would be connected. I have only included connections for the logical side of things (Path of the clock pulses) I have only shown one output leg on all three 4017 counters for clarity.

http://cliffclavin.myphotoalbum.com/view_photo.php?set_albumName=album03&id=timer1


Any help is much appreciated. Self education can be such a head ache!

Will this work as I expect it to? Any ideas welcome!

Cliff

[Kain]

I did some timers recently. I highly recommend you CMOS 4538. This thing is really accurate given you have good accurate RC, meaning within good tollerance. The C has no limit and R can be up to 1M Ohm and the formula to determine the timing interval is T=RC. This is more than simple. The chip consists of 2 independant resetable/restartable/non-restartable monovibrators that can be triggered independently, there u get 2 timers in one chip ;D. Since you were talking about CMOS chips from the beginning, just wanted to give you a hint - power your project on 12V, or anything between 7.5 and 15V. The reason why I am saying it is so it will be noise imune. You can see the thread about the problems I had before with CMOS on:

http://www.electronics-lab.com/forum/index.php?board=2;action=display;threadid=2656

CMOS is fairly easy to work with once you get what you are doing wrong ;)

[cliffclavin]

Thank you taking the time to reply - I will look into the CMOS 4538.

Thanks for ya advice about interference - your post sounded like a knightmare trying to remove interference!

The circuit will be powered by 12v dc - one of the reasons I chose the 4000 series of IC's was the 'lack of inteference' at 12v etc

I already have a prototype using two binary ripple counters and a d type flip flop (all 4000 series, up tp 17v) driven by a 555 astable. This functions perfectly and is the inspiration for this 3 stage timer.

Do you think my design will perform as expected? I am buying the parts today so fingers crossed!

[Kevin Weddle]

Just looking at your circuit makes me dizzy. I can give you a few general guidelines to use when designing logic. I don't see a clock associated with your flipflop. Flipflops can be useful but are harder to implement than a latch. Organize your circuit so that you have separated the components for easier evaluation. Avoid using the set reset if your device is a D flipflop. There is only one input with a D flipflop so you don't have to worry about the set resets. What I am getting at is the simple representation of the D flipflop where you get a logic follower if you will. Do these things and you will be much happier about your design and it will be a little easier to follower. What you have is a mess.

[cliffclavin]

Kevin Weddle : Sorry that looking at the design makes you dizzy! Thats why I wish I had electronics workbench at my disposal.

Organize your circuit so that you have separated the components for easier evaluation.

OK, I will try to make the diagram more readable.

Avoid using the set reset if your device is a D flipflop. There is only one input with a D flipflop so you don't have to worry about the set resets

The only way I know how to use D-Type flip flops is in the bi-stable mode (toggle bistable / toggle flip flop)

What you have is a mess.

Do you have anything useful to say? I am trying and am here for help, you just told me my diagram makes you dizzy, it is a mess and you don't like the way I've implemented the flip flops.

I thought using D Type flip flops in bistable mode was fine. It is listed under the basic uses of a d type flip flop here
http://www.doctronics.co.uk/4013.htm

There is only one input with a D flipflop so you don't have to worry about the set resets. What I am getting at is the simple representation of the D flipflop where you get a logic follower if you will

Could you explain this a bit more, or giva a link

I think the design is quite simple:

Timer A finishes count, sets flip flop a..
Timer B finishes count, sets flip flop b.
Timer C finishes count, Resets flip flops a & b
Timer A starts count.........

A friend checked the diagram and queried whether Counter 3 (timer 3) would be able to Reset flip flops a and b at the same time. He also suggested a fix if this was the case.

What do you all think, can Counter 3 Reset both flip flops with the same pulse?

Thanks

Cliff

[Kevin Weddle]

I am sorry if I offended you a little bit. My comments were just nonchalant and I meant it the nicest way.

[cliffclavin]

Kevin Weddle : No offence taken - I am just a tad frustrated. :) :) :)

I am re-working the diagramn to try and make it more readable.

However, an alternative soloution has been suggested without the use of the flip flops.

What do ya make of this ? :


One way is to utilize the enable input of the 4017. If the desired output is connected to the enable input, the counter will freeze when the output goes high. It can released only by reset (in what situation is starts counting from zero).

So first counter's output is connected to it's enable input and second counter's reset via an inverter. Then the first one's output is low until the counting reaches the selected output (it goes high the). Enable makes the counter freeze and releases next counter to count (not in reset situation any more). While the next counter is counting the third is held reset until the second counter reaches the seleced output value.

Then 2nd counter freezes and third is released for counting. When the third reaches the selected count, it will reset the first counter (no inverter here). The outputs for the relays are formed by combinational logic from the counter outputs. '

This sounds like a very elegant soloution. What d'ya think? Better than my original?

Many thanks,

Cliff

[cliffclavin]

I have drawn a clear diagram showing the above suggestion.

http://cliffclavin.myphotoalbum.com/view_photo.php?full=1&set_albumName=album04&id=timer999

It looks ok, but I have a question regarding counter three triggering counter one.

When the 10+ pulse comes from Counter Three, ithe pulse goes to Enable of Counter Three, So a steady signal holds Counter Three steady at 10+.

This steady signal is sent to the Reset of Counter One.

Doesnt Counter One need a short pulse to the Reset pin? Will the constant on signal from Counter Three hold Counter One in Reset Mode ?(Holding at Zero?)

So the upshot is the circuit would cycle through the three delays, then be held on permanent hold at counter one?

Or will the circuit cycle through the three delays continually?

[Guest Alun]

Well I've tried to simulate the circuit you've posted but it didn't work.

I'm going to simulate the original and see what happens.

[Guest Alun]

Tried the original to and it didn't work either - one of the outputs just stays on.

You don't need JK flip-flips because you're just using R & S so RS flip-flops will do.

Please check the circuits I've posted for errors.

[cliffclavin]

Alun, thank you very much for taking the time to help.

Pity the second soloution does not work - the schematic you provided was accurate.

However, the last schematic posted (my first idea with the flip flops) has a problem? Just to clirify my desin involved using D- Type Flip Flops.

You have connected the Reset of the first Flip Flop to a Clock.

Does the Reset of the Flip Flop (s) need to connected to the clock? There is a specific Clock input (for the D Type)

However, my first (and working!) two stage timer uses a D- Type Flipo Flop to cycle between two delays. I just used the Set / Reset pins and connected the clock input.to 0v

This design (Three stage timer) involved a Dual D Type Flip Flop, so I was gonna connect both Flip Flop Clock input to 0v, and use the Set/Reset pins, not using the Clock at all for the flip flops.

When you tested the circuit in its current format (with the erronious clock => reset connection, which side of the circuit stayed on?)

Would you be so kind as to see what happens without the clock connection to the Flip Flop reset?

Many thanks again for your help,

Cliff

[Guest Alun]

You have connected the Reset of the first Flip Flop to a Clock.

That was a mistake.

I also forgot to connect the enable to +5V.

And I was right, you only need RS flip-fllops you could make two with a 4011 cmos quad nand chip.

This circuit now works:

[Guest Alun]

By the way the left hand output is B and the right's A.

And what do you need this circuit for anyway?

There are simpler ways of doing this.

[cliffclavin]

Thank you so much for taking the time to help me! I am glad that the circuit will work as I had hoped!

will using D Type Flip flops work instead, only because I have made the order for components already... It seems a shame to place another order for one Dual RS flip flop costing 49 pence. The postage alone will be five times that!!!

The circuit I have shown here is a simplification of my idea, just to test the idea that 2 flip flops can cycle between three delays.

Instead of using one counter for each delay, I intend to use several counters in series for each delay, connected via logic 'And' gates and switches, to select a delay..

eg. Clock 1hz. 2 decades counter connected together , the 10 + connected to the Clock in of the next.

Counter 1 will have outputs 0 to 9 connected to a 1pole 10 way spst switch.
Counter 2 will have outputs 0 to 5 connected to a 1pole 6 way spst switch.

The two switch outputs are connected to an 'And' gate, whose output is connected to the flip flop.

Sorry for the pic - am terrible with mspaint!

http://cliffclavin.myphotoalbum.com/view_photo.php?set_albumName=album05&id=timeselect

Using this method, (lots of decade counters and 6 various input single pole switches) the following time periods are selectable:

Delay One = 1 to 70 secs
Delay Two = 1 to 100 mins
Delay Three = 1 to 30 mins

(Actually the circuit in the diagram above would produce a selectable time period of 11 to 70 secs. (minimum setting switch one = 1 sec, minimum setting switch two = 10 sec). I will connect lead 0 of the spst switch to the clock, load 1 of the switch to pin zero of the counter to achieve a 1 sec delay when both switches are set to there first setting etc. But this isnt shown for clarity - I was just showing my method of using switches, 'And' gates and counters in series to produce set delays of varying magnitude around the flip flops.)

That is why I have gone about this in a complicated way, so I can have an accurate, cycling, three stage selectable delay timer, with delays in the above range. Wow, what a mouthful!

Out of interest, does the 'other' idea (not using flip flops) also work, if you connect +5v to the enable in your simulator?

Can you see an easier method to do this (and cheap - the components bill was 15 pounds but I already had a few...)

Again, thank you for taking the time to help me!

Cliff

[Edit]

Because the Clock input of the flip flops will be connected to 0v, I guess I can still use the Dual D Type Flip Flop and not have to order a Dual RS FlipFlop. Correct me if I'm wrong here....

[Guest Alun]

The other idea wont work at all - the enable pins are connected to pin 9.

You can use the JK flip-flops just ground the clock and JK inputs and they will act as RS flip-flips.

A cheaper way?

A programable 8 bit counter or two programable 4 bit counters might do.

If you have access to all the programming tools a PLA would make it a lot easier to build and it might be cheaper too.