Duty Cycle control for square wave inverter

[AN920]

It appears that a lot of members are interested in building simple square wave inverters from diagrams on this forum. Problems with these designs are that the drive wave to the push pull transistors or fets does not have any dead-time or duty-cycle control. Dead time makes sure one side is turned off before the other side turn on. This is important when operating near maximum duty cycle. Also by varying the duty we can to some extent control the final output voltage of the inverter as this is set by : Vin x transformer ratio x duty (or on time)

My design provides the frequency as well as the duty cycle to be set using standard CMOS parts. R2 set the output frequency from about 45-65Hz. R1 can set the duty cycle between about 5-95% although it will never be used that low. The added advantage is that with this control circuit you can now use a transformer with lower primary voltages like 6+6 or 9+9 while still using the standard 12V source. The correct Vsec is maintained by adjusting the on time.

[audioguru]

Hi AN920,
That is nice. ;D
Maybe a FET or some other voltage controlled resistance can act as a voltage regulator to replace the R2 pot to keep the average output voltage up as the inverter is loaded down, and to keep the average voltage down if the load is removed.

[AN920]

Many ways. You can also use a small AC transformer as feedback, monitor the rectified DC and together with a opto LDR adjust R1.

[AN920]

If we take the same circuit and add some injection locking it is possible to have crystal accurate frequency drive while retaining duty cycle control.

In the circuit use  a 1.6384 MHz crystal and leave out U3B for 50 Hz. Use a 3.932 MHz crystal with U3B for 60Hz operation. Both these crystals are available commercially. You may also modify the divider ratios to accommodate other crystal values.

C4 as 10nF seems to give reliable locking but you may experiment with this value. This value locked quickly and stable in simulations. This value can be increased slightly if needed. For initial adjustment you must set the frequency control slightly faster (with J1 open) than the frequency that you are locking to by a few Hz.

Last picture shows the locking process.

Top trace shows incoming 100 Hz reference to be locked against
2nd trace shows the charging cycle of the 47nF timing cap
3rd, 4th trace shows the drive outputs

Up to marker 1 it is clear that there's no sync between output pulses and incoming reference. Output frequency is high at about 63 Hz. After marker 1 the reference is connected to the 10nF cap and after a few cycles the osc is locked against the ref as shown by the edges lining up at marker 2. Output frequency after this point is now 50 Hz

Small demo video