Question for Win Hill

[Terry Given]

Wow Tim... You really have no idea who Jim is, do you?

A photo of Jim, 35 years ago: http://www.viaarena.com/htmlimages/macho.jpg

ROTFLMAO!

Cheers
Terry

 

[Terry Given]

Exactly. Lots of universities have excellent music schools, and their
professors are no doubt technically competant to perform music and to
analyze it. But how many university music professors ever write great
music?

John

Graham Downs, of NZ band The Verlaines, submitted one of his albums for
his doctoral thesis in music at Canterbury university. Most unusual.

Cheers
Terry

 

[Terry Given]

I read in sci.electronics.design that BFoelsch <[email protected]



Yes, quite so. I was getting frustrated earlier to day over the delay in
plotting some graphics, until I realised I was asking my PC assistant to
do 4 x 4 x 4 x 100 x 100 evaluations of an eight-term expression. For
four different plots. Luckily, I could reduce the 100 x 100 to 50 x 50
without unacceptable loss of resolution.

Back when I used to build motor controllers, we hired a PhD to replace
the last PhD, doing field-oriented motor control simulations. The first
guy used to read the paper a lot, as his simulations were extremely
lengthy. The new guy convinced the boss to spend about $100,000 on some
fancy D-space hardware, to allow simulink to actually run real IGBTs and
motors, as the simulations were way too slow. I was working out my
notice (read as: doing bugger all) before heading the the US, and had
recently finished a masters paper in motor control, so I looked into the
simulation code.

I made myself very unpopular by writing a report clearly detailing why
the $100,000 was a total waste of money. Turns out the simulation built
a 4x4 matrix of expressions, and inverted it EVERY time step. Inverting
the matrix by hand, then calculating the resultant terms each time step
reduced the simulation time by an order of magnitude. Taking it further,
only 4 of the 16 terms in the inverse matrix changed each time step, the
other 12 could be pre-computed. All up the modified simulation ran 40
times faster, at a total cost of 2 hours of my time - 5hr simulations
now took about 8 minutes.

Needless to say the PHB spent the $100,000. It then took 2 guys about 6
months before they got the damn thing working. In the immortal words of
Forrest Gumps mom: "Stupid is as stupid does"

Cheers
Terry

 

[Terry Given]

I read in sci.electronics.design that BFoelsch <[email protected]



Introduce the others to 1111 0000 1111 1111!

ROTFLMAO! Well said.

Cheers
Terry

 

[Terry Given]

Usually we just design something, lay out a proper production-quality
pc board, release the documents, let manufacturing build us a first
article, and we test that. You're going to have to do that sooner or
later, and sooner gets the project that much further along. Multilayer
boards and parts are a lot cheaper nowadays than an engineer's time,
and breadboarding complex surface-mount stuff just isn't feasible any
more. We seem to simulate only tiny snippets of circuits, often just
passive r-l-c gidgets, and not whole functional circuits.

I see too many people wasting time Spicing and not thinking, and
fiddling with the simulation (and the part models!) until they think
it works. That teaches some very bad habits.

I did a tour of the Cornell EE department; PC screens outnumber
oscilloscope screens by maybe 20:1.

John

Its cheaper that way. Shame about the quality (or lack thereof) of
graduates though.

Cheers
Terry

 

[Terry Given]

I read in sci.electronics.design that John Larkin <[email protected]>



Heresy!!!!!

By all means reduce the transformer, but the filter caps MUST be each
100000000 uF, military grade, gold-plated if you can't get mithril, and
at least six in parallel.

ROTFLMAO!

For optimum audio quality, the Mithril caps need terminals made from
unobtanium, or at least expensivium. Jim's (hopefully patented) rolling
pin technique is great for removing oxygen from PCBs, but the rolling
pin must likewise be unobtanium.

Cheers
Frodo

 

[John Woodgate]

I read in sci.electronics.design that Terry Given <[email protected]>

Graham Downs, of NZ band The Verlaines, submitted one of his albums for
his doctoral thesis in music at Canterbury university. Most unusual.

Was it accepted, though?

 

[Kryten]

Well, you have pointed up a related, but separate issue; people who
somehow
think that a engineering degree is the goal, separate and apart from the
study and knowledge it takes to achieve it.

<snip>

I must admit many of my analogue design knowledge is rather rusty too.

However the thing that has stuck is an intuitive memory of how components
behave and if I don't know something then I will have an idea of what I need
to find out and be able to swot up on it promptly.

absolutely flabbergasted at the number of recent graduates who ...

... know less after university than we knew before?

My colleague interviews people and a typical question is
"how would you write a program to count the number of set bits in an integer
value?"
and many candidates haven't a clue.

ladder logic

Well it does get harder and slower to learn as one ages.

If you can do the job promptly in language X then fair enough.

Though if they can't see how ladder logic works that is a worry!

On the other hand, my mate wrote a load of test scripts and his boss wanted
him to re-write them in TCL for no other reason than that it was his
favourite language. My mate had to argue very hard indeed to point out what
a waste of time it would be.

efficient way is rejected, because it involves learning something new.

Hmm, I'm not keen on learning Verilog after learning VHDL.
It's annoying that everything seems to polarize into two antagonistic camps:
protestants/Catholics, Arabs/Jews, big/little endian, Verilog/VHDL,
C/Pascal...

At least engineers and scientists don't murder each other on engineering
differences.

Now, this is not to condemn all recent graduates. Many are indeed
excellent.
Now that I think of it, I guess what I am complaining about is the number
of
recent graduates who apparently studied "to pass the test," rather than to
learn the material, and who got away with it for four years.

It used to be that a degree certified that you had a particular level of
knowledge and ability.
Employers knew that this would sift potential employees.

Now that academia is ranked as per the qualifications they award, they have
cheated by making the exams easier. Where I got an MSc, most of us worked
hard and well to understand the course and pass the exams. What annoyed me
was that the really useless people passed too. People who couldn't even
speak/read conversational English, or understand rudimentary computing.

Perhaps there should be industry-qualified exams. That way you have to
convince professional engineers you are fit to be in their rank, rather than
some bureaucrat who will rubber stamp your degree just to make his
establishment improve their statistics.

 

[Jim Thompson]

On Sun, 02 Jan 2005 22:42:23 GMT, "Kryten"

[snip]

It used to be that a degree certified that you had a particular level of
knowledge and ability.
Employers knew that this would sift potential employees.

Now that academia is ranked as per the qualifications they award, they have
cheated by making the exams easier. Where I got an MSc, most of us worked
hard and well to understand the course and pass the exams. What annoyed me
was that the really useless people passed too. People who couldn't even
speak/read conversational English, or understand rudimentary computing.

Perhaps there should be industry-qualified exams. That way you have to
convince professional engineers you are fit to be in their rank, rather than
some bureaucrat who will rubber stamp your degree just to make his
establishment improve their statistics.

Companies are not totally ignorant... many that I know of now apply
ranking to universities... for instance MIT's BSEE ranks well above
the MSEE of most universities.

For that matter, the universities are getting smarter as well... high
schools are ranked to qualify applicants... one school's "A" is
another school's "C".

(I interview high school applicants in the Phoenix area as part of the
admissions process to MIT.)

...Jim Thompson

 

[mc]

Hmm, I'm not keen on learning Verilog after learning VHDL.
It's annoying that everything seems to polarize into two antagonistic
camps:
protestants/Catholics, Arabs/Jews, big/little endian, Verilog/VHDL,
C/Pascal...

At least engineers and scientists don't murder each other on engineering
differences.

Thank God I'm an atheist! <guffaw!>

Has anybody ever been murdered by an atheist?

 

[Kryten]

Companies are not totally ignorant... many that I know of now apply
ranking to universities... for instance MIT's BSEE ranks well above
the MSEE of most universities.

It ticks me off that companies are having to do this ranking and sifting
which the university system is paid to do but are not actually doing.

It ticks me off that someone might do a decent lot of work at one university
only to find the degree is worth very little because they grant them to
people who don't.

It used to be that a 2.2 was a decent degree, and even a 3rd didn't rule you
out if you had a plausible excuse. Most universities could be considered
'respectable'.

Nowadays job ads frequently state that you must have 2.1 or higher from a
'respected' university.

For that matter, the universities are getting smarter as well...
high schools are ranked to qualify applicants...
one school's "A" is another school's "C".

We in the UK have a couple of independent exam boards to make ratings
uniform and independent of schools. Is it not the same in the US?

(I interview high school applicants in the Phoenix area as part of the
admissions process to MIT.)

You must meet some real pointy-haired applicants...

Got any stories about the dumbest applicants you've interviewed?

 

[Keith Williams]

Well, you have pointed up a related, but separate issue; people who somehow
think that a engineering degree is the goal, separate and apart from the
study and knowledge it takes to achieve it.

In my retirement, I work part time as an instructor, teaching primarily PLC
techniques and programming. Every now and again we get into a discussion
that involves some sort of engineering calculation, for example, we might be
discussing the issue of leakage current through an output module. I am
absolutely flabbergasted at the number of recent graduates who do not
remember the formula for capacitive reactance, because they "learned it four
years ago," or even better,, those who aren't comfortable with numbering
systems and codes. I would guess that 10% of the students I get are
comfortable with the fact that FFFFh equals 1111 1111 1111 1111 binary
and -1 decimal, without using a calculator to do the conversions.

Or 65535 decimal. You didn't say what "codes" you were using. ;-)

Twenty years ago I taught as an adjunct professor at a "local" (I've
move since) four-year college. The course I generally taught was an
"introduction" to microprocessors, where we used PeeCees and MASM for
lab assignments throughout the semester. I was rather surprised when I
found that 80% of my class couldn't convert from binary to decimal by
hand and perhaps 5% could write an algorithm so the computer would do
it (thinking as a binary machine, rather than "decimal" human).

During one memorable "review session" before an exam, I got sucked into
the discussion of the difference between "add" and "or". They both use

Another interesting attitude I frequently encounter, which may be peculiar
to the PLC situation, is the desire to fit square pegs into round holes
because "I really understand square pegs." Most American PLCs use, among
others, a form of programming called ladder logic, which is dead simple and
is in reality "Visual Boolean." Ladder is great for what used to be called
"Mickey Mouse Logic," manipulating messy truth tables one bit at a time.
Many PLCs also support other languages; structured text, which is frequently
similar to Pascal (!!), Function Blocks, Grafcet, Sequential Function
Chart, etc. etc. Each has a sweet spot. What is absolutely amazing is the
number of recent graduates who want to do everything in Structured Text,
because they are good at C++. The fact that there is a simpler, more
efficient way is rejected, because it involves learning something new.

I've heard of ladder logic in traffic controls, but have never seen it.
I somehow don't think it would help with what I do, any more than
Greek. ;-)

Now, this is not to condemn all recent graduates. Many are indeed excellent.
Now that I think of it, I guess what I am complaining about is the number of
recent graduates who apparently studied "to pass the test," rather than to
learn the material, and who got away with it for four years.

I studied to learn the material and so I could play. My GPA showed it.

 

[Jim Thompson]

[snip]

For that matter, the universities are getting smarter as well...
high schools are ranked to qualify applicants...
one school's "A" is another school's "C".

We in the UK have a couple of independent exam boards to make ratings
uniform and independent of schools. Is it not the same in the US?

Just in the State of Arizona we have HUNDREDS of local school boards.
LOCAL control of schools is common throughout the USA.

The only things tying the country together are the College Entrance
Exams... SAT and ACT.

You must meet some real pointy-haired applicants...

Not really. Just some that are so nerdy/geeky that they're recluses.

Got any stories about the dumbest applicants you've interviewed?

I've been doing this for around 20 years, and can only recall one
really dumb one...

A girl showed up in her cheerleader uniform, chewing on bubble gum ;-)
She didn't even have a clue as to what MIT was all about... just that
someone told her she should apply.

...Jim Thompson

 

[mc]

A girl showed up in her cheerleader uniform, chewing on bubble gum ;-)
She didn't even have a clue as to what MIT was all about... just that
someone told her she should apply.

Ah! "It would look good on your resume." She must have gone to a prep
school that specializes in making third-rate people look second-rate. When
a first-rate, self-motivated person gets into such a school, it can be a
frustrating experience.

If you're a Gilbert and Sullivan fan, you'll recognize what I've been
muttering a parody of:

"I am a perfect specimen of prep-school mediocrity,
I only finish courses if my grade's no lower than a B,
I live a life of things that all will look good on my resumeeee...
I am a perfect specimen of prep-school mediocrity!"

 

[Kryten]

A girl showed up in her cheerleader uniform, chewing on bubble gum ;-)
She didn't even have a clue as to what MIT was all about...
just that someone told her she should apply.

<chortle>

I guess that someone was being sarcastic and she didn't get the joke...

 

[John Larkin]

I read in sci.electronics.design that John Larkin <[email protected]>


Or in proper SI symbols (too bad about the ohm!):

1 K/W == 1 ohm

1 W == 1 A

1K == 1 V

1 s == 1 s

1 gm Al == 1 F

I stand corrected. And annoyed.

John

 

[mc]

<chortle>

I guess that someone was being sarcastic and she didn't get the joke...

Bingo!

 

[John Woodgate]

I read in sci.electronics.design that John Larkin <jjlarkin@highSNIPland
THIStechPLEASEnology.com> wrote (in <hu6jt0ll3hqo4enlodf68jabro5u82a4jm@
4ax.com>) about 'Question for Win Hill', on Mon, 3 Jan 2005:

I stand corrected. And annoyed.

I didn't mean to annoy you, but it's the same as grammar and spelling,
with the difference that if you see an unfamiliar symbol, you may not
even be able to guess what it should be, unlike a wrongly-spelled word.

I was also bugged by the wrong usage of symbols in Spice (M for milli, K
for kilo, Meg for mega and Sec for second). Especially M for mill -
errors of nine orders of magnitude tend to have dramatic effects!

 

[Winfield Hill]

Jim Thompson wrote...

Well, then surely you'll want viable Spice MOSFET models, because
you'll be using the FETs throughout their useful linear range, and
the output-stage crossover region is critical.

Sadly most standard Spice library VMOS models simply don't do the
subthreshold linear region. For example, see the 10-decade plots
on page 123 of our book. A jellybean 2n7000 is rather similar to
the VN01 that we show in figure 3.14, and certainly a proper Spice
model should be able to make that plot. But I'd be surprised if
your standard Spice libraries work properly below say 5 to 20mA,
which is not that far below the FET's maximum current. Keep in
mind that linear power FET circuitry always operates well below
the maximum rated FET switching current, to keep power dissipation
junction heating under control.

The bottom line is you'll have to start your FET-amplifier design
exercise by designing some decent FET models. Let us know what you
come up with.

Win, Here's a bunch of models. Which would you recommend?

Anasoft-1:

.SUBCKT 2N7000/PLP_XN _ssi_pin0_1 _ssi_pin1_2 _ssi_pin2_3
Cgs 2 3 12.3E-12
V_ssi_pin2 _ssi_pin2_3 3 0
V_ssi_pin1 _ssi_pin1_2 2 0
V_ssi_pin0 _ssi_pin0_1 1 0
Cgd1 2 4 27.4E-12
Cgd2 1 4 6E-12
M1 1 2 3 3 MOST1
M2 4 2 1 3 MOST2
D1 3 1 Dbody
.MODEL MOST1 NMOS(Level=3 Kp=20.78u W=9.7m L=2u Rs=20m Vto=2 Rd=1.186)
.MODEL MOST2 NMOS(VTO=-4.73 Kp=20.78u W=9.7m L=2u Rs=20m)
.MODEL Dbody D(Is=125f N=1.023 Rs=1.281 Ikf=18.01 Cjo=46.3p M=.3423
+ Vj=.4519 Bv=60 Ibv=10u Tt=161.6n)
.ENDS

Anasoft-2:

.SUBCKT 2N7000_XN _ssi_pin0_3 _ssi_pin1_4 _ssi_pin2_5
* Nodes D G S
V_ssi_pin2 _ssi_pin2_5 5 0
V_ssi_pin1 _ssi_pin1_4 4 0
V_ssi_pin0 _ssi_pin0_3 3 0
M1 3 2 5 5 MOD1
RG 4 2 343
RL 3 5 6E6
C1 2 5 23.5P
C2 3 2 4.5P
D1 5 3 DIODE1
*
.MODEL MOD1 NMOS VTO=2.474 RS=1.68 RD=0.0 IS=1E-15 KP=0.296
+CBD=53.5P PB=1 LAMBDA=267E-6
.MODEL DIODE1 D IS=1.254E-13 N=1.0207 RS=0.222
.ENDS 2N7000

Supertex

.MODEL 2N7000 NMOS (LEVEL=3 RS=0.205 NSUB=1.0E15
+DELTA=0.1 KAPPA=0.0506 TPG=1 CGDO=3.1716E-9
+RD=0.239 VTO=1.000 VMAX=1.0E7 ETA=0.0223089
+NFS=6.6E10 TOX=1.0E-7 LD=1.698E-9 UO=862.425
+XJ=6.4666E-7 THETA=1.0E-5 CGSO=9.09E-9 L=2.5E-6
+W=0.8E-2)
.ENDS

Philips:

.SUBCKT 2N7000/PLP 1 2 3
Cgs 2 3 12.3E-12
Cgd1 2 4 27.4E-12
Cgd2 1 4 6E-12
M1 1 2 3 3 MOST1
M2 4 2 1 3 MOST2
D1 3 1 Dbody
.MODEL MOST1 NMOS(Level=3 Kp=20.78u W=9.7m L=2u Rs=20m Vto=2 Rd=1.186)
.MODEL MOST2 NMOS(VTO=-4.73 Kp=20.78u W=9.7m L=2u Rs=20m)
.MODEL Dbody D(Is=125f N=1.023 Rs=1.281 Ikf=18.01 Cjo=46.3p M=.3423
+ Vj=.4519 Bv=60 Ibv=10u Tt=161.6n)
.ENDS

Ancient MicroSim:

.model M2n7000 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2
+ Vmax=0 Xj=0 Tox=2u Uo=600 Phi=.6 Kp=1.073u W=.12 L=2u Rs=20m
+ Vto=1.73 Rd=.5489 Rds=48MEG Cgso=73.61p Cgdo=6.487p Cbd=74.46p
+ Mj=.5 Pb=.8 Fc=.5 Rg=546.2 Is=10f N=1 Rb=1m)

Zetex:

.SUBCKT M2N7000/ZTX 3 4 5
* Nodes D G S
M1 3 2 5 5 MOD1
RG 4 2 343
RL 3 5 6E6
D1 5 3 DIODE1
.MODEL MOD1 NMOS VTO=2.474 RS=1.68 RD=0.0 IS=1E-15 KP=0.296
+CGSO=23.5P CGDO=4.5P CBD=53.5P PB=1 LAMBDA=267E-6
.MODEL DIODE1 D IS=1.254E-13 N=1.0207 RS=0.222
.ENDS[/QUOTE]

OK, I've gotten my computer running again, wheew! and will try to
find the time to evaluate these six interesting 2n7000 spice models.

 

[Richard the Dreaded Liberal]

<chortle>

I guess that someone was being sarcastic and she didn't get the joke...

Maybe someone was being even more subtly sarcastic and Jim didn't get the
joke....

;-)
Rich