when i compile code I am getting following error
line if (ld==1) q4 <= d4;
Error (10137): Verilog HDL Procedural Assignment error at core_v.v(70): object "q4" on left-hand side of assignment must have a variable data type
module core_v(clk,ld,d0, q0,d1,d2,q1,q2,a,b,z,sel,d,q,d3,q3,d4,q4 )...