AN920

This would be a very easy task for a micro like a PIC or the like

If you read the description you will notice a) One adjustment to set the output operating frequency for 50 or 60 Hz inverter b) One adjustment to set the on-time of each device. On-time can't be more than 50% of total inverter cycle time because of push-pull operation. If you use the crystal option your output operating frequecy will be fixed at 50 or 60 Hz. The waveforms I included shows 1. Drive for a normal fixed duty cycle square wave inverter 2. Typical drive for a modified fixed duty cycle square wave inverter 3. Example of small duty cycle available from circuit. The advantage of having the adjustable duty cycle allows the use of transformers with non standard winding ratio's and a range of power supplies other than 12V. It also allows you to adjust the final output voltage. Good reading http://powerelectronics.com/mag/608PET21.pdf

This is worth a try. I have not tested it *-------------------------------------------- * NO-FRILLS LM386 MODEL * Dave Dilatush 5/30/95 * PSPICE analysis statements: .probe .ac dec 20 1 1e7 .tran 1u 3m 0 5u * circuit to test the lm386 model: vsupply vcc 0 dc 9 vsignal input 0 ac 1 sin 0 .05 1k csnub output snub .05uf rsnub snub 0 10 ccoupling output speaker 1000uf rspeaker speaker 0 8 xamp input nc1 nc2 nc3 nc4 output vcc 0 lm386 *cgain nc3 nc4 10uf ;gain boost capacitor *cbypass nc2 0 50uf ;bypass cap for PSRR * lm386 subcircuit model follows: * IC pins: 2 3 7 1 8 5 6 4 * | | | | | | | | .subckt lm386 inn inp byp g1 g8 out vs gnd * input emitter-follower buffers: q1 gnd inn 10011 ddpnp r1 inn gnd 50k q2 gnd inp 10012 ddpnp r2 inp gnd 50k * differential input stage, gain-setting * resistors, and internal feedback resistor: q3 10013 10011 10008 ddpnp q4 10014 10012 g1 ddpnp r3 vs byp 15k r4 byp 10008 15k r5 10008 g8 150 r6 g8 g1 1.35k r7 g1 out 15k * input stage current mirror: q5 10013 10013 gnd ddnpn q6 10014 10013 gnd ddnpn * voltage gain stage & rolloff cap: q7 10017 10014 gnd ddnpn c1 10014 10017 15pf * current mirror source for gain stage: i1 10002 vs dc 5m q8 10004 10002 vs ddpnp q9 10002 10002 vs ddpnp * Sziklai-connected push-pull output stage: q10 10018 10017 out ddpnp q11 10004 10004 10009 ddnpn 100 q12 10009 10009 10017 ddnpn 100 q13 vs 10004 out ddnpn 100 q14 out 10018 gnd ddnpn 100 * generic transistor models generated * with MicroSim's PARTs utility, using * default parameters except Bf: .model ddnpn NPN(Is=10f Xti=3 Eg=1.11 Vaf=100 + Bf=400 Ise=0 Ne=1.5 Ikf=0 Nk=.5 Xtb=1.5 Var=100 + Br=1 Isc=0 Nc=2 Ikr=0 Rc=0 Cjc=2p Mjc=.3333 + Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n + Tf=1n Itf=1 Xtf=0 Vtf=10) .model ddpnp PNP(Is=10f Xti=3 Eg=1.11 Vaf=100 + Bf=200 Ise=0 Ne=1.5 Ikf=0 Nk=.5 Xtb=1.5 Var=100 + Br=1 Isc=0 Nc=2 Ikr=0 Rc=0 Cjc=2p Mjc=.3333 + Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n + Tf=1n Itf=1 Xtf=0 Vtf=10) .ends *----------end of subcircuit model----------- .end *-------------------------------------------- * NO-FRILLS LM386 MODEL * Dave Dilatush 5/30/95 * PSPICE analysis statements: .probe .ac dec 20 1 1e7 .tran 1u 3m 0 5u * circuit to test the lm386 model: vsupply vcc 0 dc 9 vsignal input 0 ac 1 sin 0 .05 1k csnub output snub .05uf rsnub snub 0 10 ccoupling output speaker 1000uf rspeaker speaker 0 8 xamp input nc1 nc2 nc3 nc4 output vcc 0 lm386 *cgain nc3 nc4 10uf ;gain boost capacitor *cbypass nc2 0 50uf ;bypass cap for PSRR * lm386 subcircuit model follows: * IC pins: 2 3 7 1 8 5 6 4 * | | | | | | | | .subckt lm386 inn inp byp g1 g8 out vs gnd * input emitter-follower buffers: q1 gnd inn 10011 ddpnp r1 inn gnd 50k q2 gnd inp 10012 ddpnp r2 inp gnd 50k * differential input stage, gain-setting * resistors, and internal feedback resistor: q3 10013 10011 10008 ddpnp q4 10014 10012 g1 ddpnp r3 vs byp 15k r4 byp 10008 15k r5 10008 g8 150 r6 g8 g1 1.35k r7 g1 out 15k * input stage current mirror: q5 10013 10013 gnd ddnpn q6 10014 10013 gnd ddnpn * voltage gain stage & rolloff cap: q7 10017 10014 gnd ddnpn c1 10014 10017 15pf * current mirror source for gain stage: i1 10002 vs dc 5m q8 10004 10002 vs ddpnp q9 10002 10002 vs ddpnp * Sziklai-connected push-pull output stage: q10 10018 10017 out ddpnp q11 10004 10004 10009 ddnpn 100 q12 10009 10009 10017 ddnpn 100 q13 vs 10004 out ddnpn 100 q14 out 10018 gnd ddnpn 100 * generic transistor models generated * with MicroSim's PARTs utility, using * default parameters except Bf: .model ddnpn NPN(Is=10f Xti=3 Eg=1.11 Vaf=100 + Bf=400 Ise=0 Ne=1.5 Ikf=0 Nk=.5 Xtb=1.5 Var=100 + Br=1 Isc=0 Nc=2 Ikr=0 Rc=0 Cjc=2p Mjc=.3333 + Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n + Tf=1n Itf=1 Xtf=0 Vtf=10) .model ddpnp PNP(Is=10f Xti=3 Eg=1.11 Vaf=100 + Bf=200 Ise=0 Ne=1.5 Ikf=0 Nk=.5 Xtb=1.5 Var=100 + Br=1 Isc=0 Nc=2 Ikr=0 Rc=0 Cjc=2p Mjc=.3333 + Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n + Tf=1n Itf=1 Xtf=0 Vtf=10) .ends *----------end of subcircuit model----------- .end

The designer thought if the cap can work for a 555 it should be good for this as well :)

http://www.jiggybyte.com/IndexAnon.php

I think you are missing the whole point.

It shows that you can have much better control over the output that a fixed duty cycle drive.

That part model (7447) in Multisim is known to be faulty over a few issues. Even in the latest release it is still not working. They never bothered to fix it. Use a 74HC4543 or 4543 to get it working

Also look what I described in this post http://www.electronics-lab.com/forum/index.php?topic=10858.0

From the latest EDN magazine "Cheap and easy inductance tester uses few components" full article here http://redigitaleditions.com/Repository/EDN/2007/04/12/EDN070412.pdf#OLV0_Page_0111

All those XNOR's form the pulse multiplier. I will post a version with a VCO multiplier as well but the multiplying range will be limited. You can pick the one that looks more simple and suit your purpose. If you make R4 adjustable you can trim it for the range you want

Maybe it is just a glitch in the system. As long as you are logged in you should be able to view the files.

Nick this may work. SW1 gives 2 modes. With SW1 closed you can set the output frequency from (2 MHz/9999)/2 =100.01Hz to (2 MHz/999)/2 = 1001 Hz With SW1 open the output will start at 1000.1 Hz to 10010 Hz (range above multiplied by 10). You can get a much higher frequencies with the switch settings lower than 999 I have used a hardware digital x 10 pulse multiplier instead of a typical VCO type because it does not need special adjustments and operate over a much wider range. U7 will provide the 50% duty cycle you required. You can make the switch selection easy by driving that lines with your uP which can do all the calculations for you. DSW1 will be your MSD and DSW4 your LSD. RP1,2 is respacks with 8 x 100k pull-up resistors. VDD should be 10-15V I have not simulated the whole design as I don't have a model for U6. It is up to you to try. I have included the way the multiplier works. Each edge generates 5 pulses

http://www.ortodoxism.ro/datasheets/panasonic/SJC00104CED.pdf

This little circuit will produce sine waves with less than 1% distortion over a wide range. Between 20-20Khz distortion is less than 0.8% Needs 8-10Vp-p triangle wave input and will produce a 2Vp-p sine output. Simulation results shown at 1KHz. R5 and R3 must be set for lowest distortion. After setting it will be good for the whole range provided input amplitude remains constant. Circuit will not work well with all types of jfet's. Works well also with BF256B or jfet with similar Idss

Maybe to do something with rate multipliers. I have done something in the past and must just remember how I did it and find the diagrams. Look at this also http://www.linear.com/pc/downloadDocument.do?id=5084

Are you ok with steps of 0.1Hz from 100 Hz to 999.9 Hz and then 1 Hz steps from 1000 to 9999 Hz?

I removed the last post after I realized that as you divide by a lower count you will be stepping in larger increments of course! The math can be easily solved with a uP. I will give it a bit more thought and post something that looks workable.

One way to do it is make a frequency synth with a range 1000 - 100000 Hz that can be incremented 1 Hz. Then divide the output by 10 to give a range of 100.0 - 10000 This can be under uP control or BCD thumbwheel switches Look at the CD4059 it may just what you are looking for http://www.ee.washington.edu/stores/DataSheets/cd4000/cd4059.pdf

What you are saying does not make any sense.

Connect that to your input pulse you want to count. It won't count on its own. The count pulse must be a logic level input

One should always remember that SPICE type simulators like the LT assume perfect components. In real life the Q of coils and capacitors at the operating frequency makes a big difference. A more accurate simulation will be with a simulator that use harmonic balance techniques and simulate transistor operation under non-linear conditions using non-linear models. These simulators also use very accurate models for the passive components. SPICE simulators are intended for time domain and not suited for frequency domain analysis.

If we take the same circuit and add some injection locking it is possible to have crystal accurate frequency drive while retaining duty cycle control. In the circuit use a 1.6384 MHz crystal and leave out U3B for 50 Hz. Use a 3.932 MHz crystal with U3B for 60Hz operation. Both these crystals are available commercially. You may also modify the divider ratios to accommodate other crystal values. C4 as 10nF seems to give reliable locking but you may experiment with this value. This value locked quickly and stable in simulations. This value can be increased slightly if needed. For initial adjustment you must set the frequency control slightly faster (with J1 open) than the frequency that you are locking to by a few Hz. Last picture shows the locking process. Top trace shows incoming 100 Hz reference to be locked against 2nd trace shows the charging cycle of the 47nF timing cap 3rd, 4th trace shows the drive outputs Up to marker 1 it is clear that there's no sync between output pulses and incoming reference. Output frequency is high at about 63 Hz. After marker 1 the reference is connected to the 10nF cap and after a few cycles the osc is locked against the ref as shown by the edges lining up at marker 2. Output frequency after this point is now 50 Hz Small demo video

Do you want to use it for ultrasonic transducer? Transducer will work with square wave as well.

Many ways. You can also use a small AC transformer as feedback, monitor the rectified DC and together with a opto LDR adjust R1.