Altera Announces Hardware and Software Updates for Enhanced FPGA Development
The newest updates include FPGA devices with increased logic density and improved memory interfaces, as well as updated software to streamline FPGA design in edge AI and 5G/6G wireless applications.
At its recent Innovators Day developer conference, Altera announced several updates to its Agilex FPGA and SoC families, focused on enhanced performance for demanding applications. The company has made all Agilex FPGA and SoC FPGA device families available for production. A key highlight of the announcement is the beta release of the Visual Designer Studio tool in Altera’s newest version of its Quartus Prime FPGA design software.
At its Innovators Day 2025, Altera unveiled expansions to the Agilex 5 FPGA and Agilex 3 SoC FPGA product families to deliver greater performance and power in modern applications like edge AI and 5G/6G wireless. Image used courtesy of Altera
Agilex FPGA Portfolio Expansion
A significant technical update is the expansion of the mid-range Agilex 5 and Agilex 3 SoC FPGAs. Altera has increased the logic density of these devices by up to 2.5 times, with the highest-density parts now offering up to 1.6 million logic elements. This enhancement aims to address the growing computational needs of applications such as edge AI inference, 4K/8K video processing, and next-generation 5G/6G wireless radio infrastructure.
In addition to logic density improvements, Altera has boosted the memory interface speeds across all Agilex 5 D-Series FPGAs. The new specifications show a 25% increase, with DDR5 interface speeds now reaching 5,600 MT/s and LPDDR5 speeds at 5,500 MT/s. These higher speeds are critical for systems requiring high-bandwidth memory access, a common requirement in data-intensive tasks like those found in machine learning and video processing.
Altera has added post-quantum cryptography (PQC) secure boot capability to its Agilex 5 D-series devices for enhanced protection. Image used courtesy of Altera
Security features have also been a focus. All Agilex 5 D-Series devices now include a post-quantum cryptography (PQC) secure boot capability. This feature provides a layer of defense against potential future cryptographic attacks, an increasingly important consideration for embedded systems and connected devices.
Quartus Prime Software Version 25.3
Beyond hardware, Altera also released Quartus Prime Software version 25.3. This new software release introduces an early access version of a new system integration tool called Visual Designer Studio. The tool is designed to automate the process of connecting IP blocks, which can simplify the design flow and shorten the time required to begin a new FPGA project.
According to Altera, the new software version shows a 6% improvement in compile times over version 25.1.1 and an average reduction of 6% in the use of adaptive logic modules (ALMs). The combined hardware and software improvements are intended to provide a more streamlined and efficient development experience.
Altera currently offers a beta version of its Visual Designer Studio, part of the Quartus Prime Pro Edition software version 25.3. Image used courtesy of Altera
Enhancing FPGA Design and Development
The latest updates to Altera’s Agilex portfolio center on scaling performance and improving the development workflow. The increased logic density and faster memory interfaces of the Agilex 5 D-Series FPGAs target high-performance computing support. The inclusion of post-quantum cryptography enhances device security, while the new Visual Designer Studio tool in Quartus Prime aims to simplify IP block integration. These advancements are well-suited for a variety of demanding applications, including high-resolution video encoders and decoders, complex edge AI inference systems, and next-generation wireless radio units.
I wish Quartus would feature a decent editor. The current would be fine in 1992 Windows 3.1. Take a look at SW development tools such as Jetbrains CLion and VS Code which are light years ahead in terms of usability.