Microchip DSC Adds Post-Quantum Cryptography and Secure Boot
Targeting AI servers and automotive applications, this 200 MHz 32-bit controller integrates 78 ps high-resolution PWMs and dedicated hardware for post-quantum cryptography.
Microchip Technology has recently expanded its digital signal controller (DSC) portfolio with the dsPIC33AK256MPS306, adding Post-Quantum Cryptography support. As part of the dsPIC33A family, this new device is designed for high-performance, secure applications such as AI server power supplies, automotive systems, and industrial automation.
Microchip dsPIC33A DSC brings post-quantum Cryptography and real-time control to industrial and power applications.
The dsPIC33AK256MPS306 Digital Signal Controller (DSC)
Built around a 200 MHz 32-bit core, the dsPIC33AK256MPS306 includes a double-precision Floating-Point Unit (FPU) and a fixed-point DSP engine with dual 72-bit accumulators. This is combined with a wide range of high-speed analog and timing peripherals.
Block diagram of the dsPIC33AK256MPS306 showing its 200 MHz DSP core, memory architecture, high-speed peripherals, and integrated security/crypto modules.
Key technical highlights include:
- High-Resolution PWMs: The device includes multiple high-resolution PWM modules with up to 78 picoseconds (ps) fine edge placement accuracy. This level of precision is important for controlling modern wide-bandgap semiconductor drivers for devices like silicon carbide (SiC) and gallium nitride (GaN), which operate at high switching speeds.
- High-Speed Data Acquisition: For fast control loops, the controller integrates three 12-bit ADCs running at up to 40 MSPS, along with up to five high-speed comparators with 5 ns response time.
- Advanced Connectivity: It offers a wide range of peripherals, including CAN FD, I3C, and a dedicated Resolver-to-Digital Converter (RDC) interface.
Cybersecurity and Functional Safety
Security is another key highlight of the dsPIC33AK256MPS306 MCU, as it includes a dedicated Crypto Accelerator Module (CAM) with support for the Commercial National Security Algorithm Suite 2.0, including recommended post-quantum cryptographic algorithms. It also features hardware support for Secure Boot, an Immutable Root of Trust (IRT), and secure firmware updates, helping protect against modern cryptographic threats in connected systems.
Furthermore, the device is designed for mission-critical functional safety and target compliance with ISO 26262 ASIL B, IEC 61508 SIL 2, and IEC 60730 Class B standards. They include built-in safety features such as Error Correcting Code (ECC) for both Flash and RAM, a Windowed Watchdog Timer (WDT), and I/O Integrity Monitors.
Images used courtesy of Microchip
