Cadence’s Tensilica HiFi iQ DSP Features Voice AI and Audio Processing
https://www.electronics-lab.com/cadences-tensilica-hifi-iq-dsp-features-voice-ai-and-audio-processing/
The new DSP IP core improves AI and audio performance with FP8/BF16 support, enhanced SIMD processing, and lower power consumption for voice-enabled embedded systems.
Cadence and Skywater Detail Next Open Multi-Project Wafer Shuttle Program
https://www.electronics-lab.com/cadence-and-skywater-detail-next-open-multi-project-wafer-shuttle-program/
The program offers cost-effective access to the 130 nm CMOS process, enabling students, researchers, and start-ups to tapeout complex mixed-signal designs using commercial-grade and open-source tools.
OMGS3 is a Compact yet Fully Functional ESP32-S3 Module
https://www.electronics-lab.com/omgs3-is-a-compact-yet-fully-functional-esp32-s3-module/
The OMGS3 is a compact, fully-featured ESP32-S3-PICO board from the Unexpected Maker. With its dual-core architecture and QSPI memory, it can effortlessly handle more than one task at a time. It has wireless connectivity supporting Wifi, Bluetooth, and an Onboard High Gain Antenna. The Architecture of the OMGS3 Board The Xtensa LX7 Core is designed […]
PSpice for TI tool offers system-level circuit simulation
https://www.electronics-lab.com/pspice-for-ti-tool-offers-system-level-circuit-simulation/
Texas Instruments (TI) has announced a new custom version of the PSpice simulator from Cadence Design Systems that enables engineers to simulate complex analog circuits with unlimited analysis of TI power and signal-chain products. By Rich Pell @ smart2zero.com Available for download at no cost, PSpice for TI offers full-featured circuit simulation with a growing […]
Imec and Cadence Tape Out Industry’s First 3nm Processor Chip
https://www.electronics-lab.com/imec-cadence-tape-industrys-first-3nm-processor-chip/
Nanoelectronics research institute IMEC and Cadence Design Systems have worked together to produce a tape-out for the industry’s first 64bit processor core as a test chip to be built in a nominal 3nm node. The tape-out project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules […]