ETH Zurich Researchers Introduces A New RISC-V based Processor Architecture

ETH Zurich Researchers Introduces A New RISC-V based Processor Architecture

For the growing demand for floating-point operations per second, a group of researchers at ETH Zurich (home for some significant RISC-V innovation) announced a new RISC-V-based processor architecture with substantial upgrades in performance and energy efficiency. The basic idea behind the innovation comes from the combination of a tiny 10kGE (kilo gate equivalent) control core, now known as Snitch, with a double-precision FPU. Since the traditional approach introduced a trade-off between the non-floating point unit area and floating-point utilization, which has been taken care of by the Snitch. This was done by enhancing the RISC-V instruction set architecture with “two minimally intrusive extensions”.

The decision to include stream semantic registers and a floating-point repetition instruction was the key to reaching the goal. These ISA extensions further reduced the pressure on the core and gave the opportunity to run other tasks which made Snitch and FPU a dual-issue at a minimal incremental cost of 3.2%. The proposed architectural modifications were carried out on an octa-core cluster of 22nm technology. The results show that the methodology achieved over 6x multi-core speed up and a 3.5x gain in energy efficiency.

The contributions made by the group of researchers include the design of a general-purpose, single-stage, single-issue core tuned for high energy efficiency which is aimed towards maximizing the compute per control ratio. The ISA extensions of the stream semantic register are meant to accelerate data oblivious problems by providing an efficient semantic to read and write from memory. An algorithm is called data-oblivious if its control flow and memory access pattern do not depend on its input data.

“We aim to maximize the control to compute ratio by providing a small and agile integer core that can make single-cycle control flow decisions and integer arithmetic and combine it with a large FPU,” the team explains. “The system offers an implementation of the RISC-V atomic extension (A) for efficient multicore programming and can be targeted with a standard RISC-V toolchain.”

The research was published in the journal IEEE Transactions on Computers under closed access terms.

[Image Credit: Hackster News]
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About Abhishek Jadhav

Abhishek Jadhav is an engineering student, RISC-V ambassador and a freelance technology and science writer with bylines at Wevolver, Electromaker, Embedded Computing Design, Electronics-Lab, Hackster, and EdgeIR.

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