Jitter No More: Skyworks Introduces Clock Buffers for High-Speed Infrastructure

In the relentless pursuit of faster data rates, system architects and electrical engineers are constantly battling a silent but critical foe: jitter. This timing variation in a clock signal can be the difference between a high-performance system and one riddled with errors. As data rates climb into the tens and hundreds of gigabits per second, the tolerance for jitter shrinks to the femtosecond range, pushing existing clocking solutions to their limits. 

Skyworks Solutions, a long-standing player in the RF and analog world, is directly addressing this challenge with its new family of ultra-low jitter clock fanout buffers, the SKY53510/80/40 series.

Skyworks’ new lineup of SKY53510/80/40 clock fanout buffers is built for use in wireless networks, data centers, and other high-speed infrastructure. Image used courtesy of Skyworks

SKY53510/80/40 Clock Fanout Buffers

Skyworks’ new SKY53510/80/40 clock fanout buffers are purpose-built for timing accuracy, featuring a low additive RMS phase jitter of just 35 femtoseconds (fs) at 156.25 MHz. For designers working on PCIe Gen 7, the jitter is even lower at just 3 fs at 100 MHz. 

One of the most significant design headaches for engineers is the need to interface different clocking formats. Systems often use a mix of signaling standards like LVPECL, LVCMOS, and HCSL. The SKY53510/80/40 family simplifies this with universal format translation. It can accept any of these input formats and provide selectable LVPECL, LVDS, and HCSL outputs, eliminating the need for external translation circuitry. The buffers also feature a 3:1 input multiplexer and can provide up to 10 differential outputs, making them versatile for complex clock tree architectures. 

Skyworks’ SKY53510 ultra-low additive jitter clock buffer features two inputs and 10 differential outputs. Image used courtesy of Skyworks

Low Power, Low Noise

Beyond performance, Skyworks has designed its new line of clock buffers with practical implementation in mind. The devices operate with separate core and output voltage supplies (1.8 V, 2.5 V, 3.3 V), and they integrate on-chip low-dropout (LDO) regulators, a crucial feature for maintaining signal integrity in noisy electrical environments. Additionally, these integrated LDOs provide a high power supply rejection ratio (PSRR), effectively filtering out noise on the power rails that could otherwise translate into jitter on the clock output.

Block diagram of the SKY53580 8-output ultra-low additive jitter clock buffer. Image used courtesy of Skyworks

Combating Jitter in High-Speed Systems

The demand for such precise timing is being driven by several key applications. 5G and 6G radio systems, for example, rely on synchronized clocks to properly handle massive amounts of data flowing through their front-end and baseband processing units. Similarly, the backbone of modern computing, the data center, is a dense network of servers and switches where every nanosecond counts. The PCIe standard, the workhorse of internal system communication, is also on a rapid trajectory toward higher speeds, with PCIe Gen 7 requiring exceptionally low jitter clocking to achieve its target data rates.

The new Skyworks clock buffers provide users with a stable, clean, and accurate clock signal. By providing a combination of ultra-low jitter performance, format flexibility, and integrated features for noise rejection, the SKY53510/80/40 series is designed to empower engineers to push the boundaries of speed and performance in everything from core network infrastructure to medical imaging systems.