Lattice’s Mach-N2 FPGAs Add Post-Quantum Security to System Control
New secure control FPGAs pair on-chip flash and quantum-resistant cryptography for long-lifecycle infrastructure designs.
Lattice Semiconductor has expanded its secure control FPGA lineup with the Mach-N2 family, a set of small-footprint devices designed for system control and security in modern compute, communications, and industrial infrastructure. Built on the company’s Nexus 2 platform, Mach-N2 folds integrated non-volatile flash, a hardware Root of Trust, and CNSA 2.0-compliant post-quantum cryptography (PQC) into a single package, giving designers a way to future-proof systems expected to stay in service for a decade or more. The family launches alongside Lattice Prompt, a new AI-assisted design tool, though the FPGAs are the headline act.
Hardened Against Tomorrow’s Threats
Post-quantum readiness sits at the center of the Mach-N2 pitch. The devices support ML-DSA, LMS, and XMSS for authentication and ML-KEM for key exchange, all aligned with the CNSA 2.0 suite. Crypto agility lets fielded systems swap in updated algorithms as standards evolve, paired with anti-rollback protection to stop attackers from reverting firmware to a weaker, previously patched state. Device identity is anchored by a physically unclonable function (PUF), with DICE and SPDM attestation confirming that both the platform and its supply chain haven’t been tampered with. Classical cryptography hasn’t been neglected either: AES-256-GCM, 521-bit ECC, and 4096-bit RSA are all accessible at runtime, and configurable anti-tamper monitoring rounds out the security stack.
Density and Speed Without the Wait
Beyond security, Mach-N2 pushes meaningful gains in raw capability. The largest device in the family reaches 220,000 system logic cells, roughly double the density of its predecessor, alongside enhanced SERDES bandwidth for direct links to modern SoCs and processors. On-chip flash keeps the configuration bitstream and user flash memory away from external probing while enabling instant-on boot: the 220k-cell part fully configures in under 30 milliseconds, a window tight enough to matter during the vulnerable moments of power-up and power-down sequencing. Designers can also store up to three configuration images (primary, secondary, and golden) for fault recovery without external intervention. Connectivity options include PCIe 4.0 and 10G Ethernet, with SERDES lanes running up to 16 Gbps.
The Mach-N2 architecture pairs its control and security blocks with embedded flash, connecting to a host processor over PCIe and to the board through GPIO. Image used courtesy of Lattice
An AI Assistant Along for the Ride
Mach-N2 designs are supported by the latest Lattice Radiant release and by Lattice Prompt, a natural-language design tool that connects to a developer’s large language model and integrated development environment of choice over the open Model Context Protocol. Prompt orchestrates Radiant in the background, handling everything from synthesis to bitstream generation while grounding its suggestions in Lattice’s own documentation and knowledge base.
Between the two announcements, Lattice is betting that quantum-resistant security and faster development cycles will matter more to system architects in the next few years than raw logic count alone. Mach-N2 samples are already in the hands of compute and communications customers, and the parts look like a natural fit for power sequencing, network switch management, and secure datapath applications where a system needs to boot fast, stay authenticated, and keep working long after today’s encryption standards have been retired.
