Digitally Controlled Audio Processor using TDA7440

This Audio Processor designed using TDA7440 chip from ST. The chip is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in Hi-Fi systems. A selectable input gain is provided. Control of all the functions is accomplished by serial bus I2C. The AC signal setting can be altered by resistor networks and switches combined with operational amplifiers.

Features

• Supply 9V DC (Range 6V to 10V)
• All functions Programmable Via I2C Serial Bus
• 4 Channel Stereo Inputs, Multiplexer, I2C Selectable
• Treble and Bass Control 2.0dB Steps
• One Channel Stereo Output
• Two Speaker Attenuators, Two Independ Speaker Control In 1.0dB Steps for Balance
• Volume Control In 1.0dB Steps
• Screw Terminals for Audio Inputs and Outputs
• Header Connector for I2C Digital Interface
• Header Connector for Power Input
• On Board Power LED
• 4 x 4MM PCB Mounting Holes
• PCB Dimensions 82.55 x 44.93 mm

TDA7440

The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7440D audio processor provides 3 bands tones control.

Treble Stage

The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and an external capacitor connected between treble pins and ground.

I2C BUS INTERFACE

Data transmission from microprocessor to the TDA7440D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).

Data Validity

As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Start and Stop Conditions

As shown in schematic a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

Acknowledge

The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 13). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.

Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from mis working.

Connections

• CN1: Pin 1 = Right Channel Audio In4, Pin 2 = GND
• CN2: Pin 1 = Right Channel Audio In3, Pin 2 = GND
• CN4: Pin 1 = Right Channel Audio In2, Pin 2 = GND
• CN6: Pin 1 = Right Channel Audio In1, Pin 2 = GND
• CN8: Pin 1 = Left Channel Audio In1, Pin 2 = GND
• CN9: Pin 1 = Left Channel Audio In2, Pin 2 = GND
• CN10: Pin 1 = Left Channel Audio In3, Pin 2 = GND
• CN12: Pin 1 = Left Channel Audio In4, Pin 2 = GND
• CN3: Pin 1 Left Channel Audio Output, Pin 2 = GND
• CN5: Pin 1 Right Channel Audio Output, Pin 2 = GND
• CN7: Pin 1 SDA Digital Pin, Pin 2 = SCL Digital Pin, Pin 3 = Digital GND
• CN11: Pin 1,2 = VCC, Pin 3,4 = GND
• D1: Power LED

Schematic

Parts List

Connections

Block Diagram

Application Diagram

Gerber View

Photos

TDA7440 Datasheet