3D memory die boasts 100+ layer design
Utilizing Samsung’s unique ‘channel hole etching’ technology, the new V-NAND adds around 40-percent more cells to the previous 9x-layer single-stack structure. This is achieved by building an electrically conductive mold stack comprised of 136 layers, then vertically piercing cylindrical holes from top to bottom, creating uniform 3D charge trap flash (CTF) cells.
As the mold stack in each cell area increases in height, NAND flash chips tend to become more vulnerable to errors and read latencies. To overcome such limitations, Samsung has incorporated a speed-optimized circuit design that allows it to achieve the fastest data transfer speed, at below 450 microseconds (μs) for write operations and below 45μs for reads. Compared to the previous generation, this represents a more than 10-percent improvement in performance, while power consumption is reduced by more than 15 percent. Thanks to this speed-optimized design, Samsung will be able to offer next-generation V-NAND solutions with over 300 layers simply by mounting three of the current stacks, without compromising chip performance or reliability.
In addition, the number of channel holes required to create a 256Gb chip density has decreased to 670 million holes from over 930 million with the previous generation, enabling reduced chip sizes and less process steps. This brings a more than 20-percent improvement in manufacturing productivity. Following this introduction, the company plans to offer 512Gb three-bit V-NAND SSD and eUFS in the second half of this year.
Samsung – www.samsung.com
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