Synopsys announces a neural processing unit IP and software toolchain
To address the increasing demands of artificial intelligence applications deployed at the edge, Synopsys has announced a neural processing unit IP to deliver high performance and support the most advanced neural network models. Overall, the new DesignWare ARC NPX6 NPU IP delivers up to 3,500 tera operations per second for automotive, consumer, and data center chip designs. The neural processing unit solves the demands of real-time computing with the low-power consumption of advanced AI applications. Also, to accelerate the software development process, Synopsys also announced the new DesignWare ARC MetaWare MX Development Toolkit for a comprehensive compilation environment with automatic neural network algorithm partitioning.
The DesignWare ARC NPX6 NPU IP scales from 4K to 96K MACs and delivers up to 250 tera operations in a single instance at 1.3GHz clock frequency on 5nm process technology. The same hardware performs up to 440 TOPs using sparsity features to increase performance and reduce energy demands for executing neural networks. The NPU integrates hardware and software connectivity features to enable the implementation of multiple NPU instances and further achieve 3,500 TOPs of performance on a single SoC.
Based on our seamless experience integrating the Synopsys DesignWare ARC EV Processor IP into our successful NU4000 multi-core SoC, we have selected the new ARC NPX6 NPU IP to further strengthen the AI processing capabilities and efficiency of our products when executing the latest neural network models, said Dor Zepeniuk, CTO at Inuitive, a designer of powerful 3D and vision processors for advanced robotics, drones, augmented reality/virtual reality (AR/VR) devices and other edge AI and embedded vision applications.
In terms of performance, the ARC NPX6 NPU IP provides more than 50x of the maximum configuration of the ARC EV7x processor IP. The ARC NPX6 NPU IP also offers optional 16-bit floating-point support inside the neural processing unit and simplifies the transition from GPUs used for AI prototyping to high volume power and area-optimized SoCs.
Higher resolution images, more cameras in systems, and more complex algorithms are driving AI processing requirements for high TOPS performance, said John Koeter, Sr. VP, marketing and strategy in the Synopsys Solutions Group. With the new DesignWare ARC NPX6 and NPX6FS NPU IP, as well as MetaWare MX Development Toolkits, designers can take advantage of the latest neural network models, meet growing performance demands and accelerate time-to-market for their next intelligent SoCs.
When it comes to the ARC MetaWare MX Development Toolkit, Synopsys has included the compiler, debugger, neural network software development kit, virtual platforms SDK, runtimes and libraries, and advanced simulation models. Specifically for automotive applications, the development toolkit includes a safety manual and safety guide to help developers meet the ISO 26262 requirements.
In addition, the easy-to-use ARC MetaWare tool helps us take maximum advantage of the processor hardware resources, ultimately helping us to meet our performance and time-to-market targets.
The DesignWare ARC NPX6 NPU IP and ARC MetaWare MX Development Toolkit will be available for the customers to use. On May 19, the company requests interested developers to attend the Synopsys Deep Dive session at the Embedded Vision Summit to learn about how to “Optimize AI Performance and Power for Tomorrow’s Neural Network Applications.”