PCB category

New parts library for Mentor PADS & DX Designer accelerates PCB design

Designers can build circuit boards faster with millions of symbols & footprints on SnapEDA.

July 18, 2017 –  SAN FRANCISCO –  Mentor, a Siemens business, and SnapEDA, the Internet’s first parts library for circuit board design, are announcing new support for Mentor PADS® and DX Designer on SnapEDA.

Whether building satellites or medical devices, hardware designers spend days creating digital models for each component on their circuit boards, a painful and time-consuming process that hinders product development.

With today’s launch, Mentor PADS & DX Designer customers will gain access to SnapEDA’s extensive component library containing millions of symbols, footprints, and 3D models, further enhancing the vast resources available for Mentor PCB design software.

All parts are auto-verified with SnapEDA’s proprietary verification technology, helping to reduce risk and unneeded, costly prototype iterations. This technology answers common questions designers have about libraries, such as “what standards does this footprint conform to?”

As the world becomes more connected, electronic devices are proliferating and diversifying, and time-to-market is more crucial than ever for companies to stay competitive.

How to Route Differential Pairs

Sam Sattel @ autodesk.com discuss about the benefits of differential signals and how to route them in Eagle.

If you’re designing a high speed PCB, then chances are you’re working with the latest and most powerful technologies, like HDMI, USB3.0, Ethernet, or DDR. But with great power comes great responsibility! As a result, you’ll likely be dealing with issues like electromagnetic interference (EMI) and noise.

So what do you do about these problems? When you’ve got a bunch of noisy signals on your board and you need a way to protect the transmission of your data then you need to be using differential pairs. In this blog we’ll be looking at all of the great benefits for using differential pairs in your high speed design project, and how to route them in Autodesk EAGLE.

How to Route Differential Pairs – [Link]

Fiducial Marks in PCBs – What they are?

In the past, I’ve  always seen small circuits of copper with no silk screen or solder mask on top of it and as a PCB designer I have always the question in my mind: What is it for? — I’ve never needed them before!

As I can find them in Arduino’s PCBs as well, I decided to open the design file and investigate more about these marks. They are called: Fiducial marks.

Fiducial Mark in Arduino UNO PCB. Original Image Courtesy of reichelt

Fiducial Mark is a circuit solder mask with a round bare copper in the center. The copper diameter is smaller than the solder mask. As the name may imply; these marks are used by assembling machines as points of reference, and they should be placed in any PCB side that has SMD components.

No restrict rule about  how many or where theses marks should be placed. But according to the reference, it’s good to position two fiducial marks on opposite corners of the PCB, and it’s advisable to put a mark near the packages with small pitch like BGA, QFN and QFP.

Image Courtesy of pcb-3d

When it comes to size of fiducial marks, it depends on the used assembly machine. The mark dimensions could be 3.2mm of solder mask opening diameter and 1.6mm diameter of bare copper or 2mm of solder mask opening diameter and 1mm diameter of bare copper.

Image Courtesy of Ladyada

I found a video on Youtube showing how Fiducial Marks are recognized in a PnP (Pick and Place) machine.

Also, I found that Ladyada made a short blog post on the problems you may face using Fiducial Marks recognition in PnPs.

PCB Design for manufacture [PDF]

SeeedStudio has published a PCB design manual to help makers and engineers design better PCBs. The guide covers many aspects of PCB design for manufacture summarizing the experience of their PCB service over the last 9 years.

PCB Design for manufacture – [Link]

Printed Two-Dimensional Transistors

Researchers from AMBER (Advanced Materials and BioEngineering Research) and Trinity College (Dublin), together with the TU Delft have succeeded in producing printed transistors, which are made solely from two-dimensional nano materials. These materials have characteristics with much promise and, importantly, can also be produced very cheaply. Possible applications for this procedure are food packaging with a digital countdown timer for the use-by date, wine labels which will show when the contents is at the optimal drinking temperature, security for bank notes and perhaps even flexible solar cells.

The researchers, under the leadership of professors Jonathan Coleman and Georg Duesberg, have used standard printing techniques to combine nano sheets of graphene, which are used as electrodes, with two other nano materials (tungsten diselenide and boron nitride) that function as channel and separator. The result is functional transistor made from nano sheets using only printing technology.

Two-dimensional transistors, as such, are not new – they have already been manufactured using a chemical deposition from the vapor phase. A significant disadvantage of this and other existing methods is their high cost. In comparison, printed electronics is based around printable molecules formed from carbon compounds, which can easily and cheaply be turned into a usable ink.

The material of the printed electronics comprises a large number of nano sheets of different sizes (which are sometimes also called ‘flakes’). During the printing process these are layered in a random pattern. The consequence of this is that the printed material is somewhat unstable and the performance has some limitations.

The transistors printed this way are a first important step towards printed 2D-structures made from a single nano sheet. This would dramatically improve the performance of printed electronics. This is the subject of current research at the TU Delft.

Jonathan Coleman from Trinity College is a partner of Graphene flagship, an EU initiative that in the next 10 years has to stimulate new technologies and innovation.

Source: Elektor

New Release For EAGLE CAD with PCB Alignment Tools

Since Autodesk acquired Eagle CAD, big changes have been made to Eagle CAD. Regardless of the new licensing system using subscription model, which was a subject to criticism by a lot of users, the new management of Eagle from Autodesk has successfully added a lot of demanding features that old team failed to bring out.

Eagle 8 came with a lot of new features like BGA auto-router and “Past Block Design” tool to add a complete block of connected components both in schematic and board.

The new release 8.1.1 brought PCB alignment tool to align a group of objects in different positions; top, bottom, left, right, center, and distribute horizontally / distribute vertically.

Image Source: Autodesk Eagle’s Forum

Another improvement in eagle 8.1.1 that deserves mention is that a new category has been added to DRC (Design Rule Check) called Airewire. It’s an important improvement because airwires is one of the most common things designer should be aware of. In older Eagle releases, you should work with your eyes wide open and never forget to hit ratsnest at the end of your work and read the magic sentence in the bottom corner “Ratsnest: Nothing to do !”.

Image Source: Autodesk Eagle’s Forum

Source: Autodesk Eagle’s Forum

Exploring Eagle CAD ULPs #6 – Group-aps_v4.ULP Autoplace by Group

Welcome to the 6th post of the “Exploring Eagle CAD ULPs” series. Each post will be discussing one useful ULP in Eagle CAD.

“ULP” User Language Program is a plain text file which is written in a C­-like syntax and can be used to access the EAGLE data structures and to create a wide variety of output files. You can think about it as a plug-in for Eagle.

You can reach the posts published in this series using the following link.

In the previous post we explored Place50 ULP which places all parts of the board to the position in the schematic. Place50 moves all parts of the board, but sometimes we need to do this auto-placement for just a certain group of parts. Beside that, we can’t change the position scaling factor in Place50. Group-aps_v4 ULP overcomes these two points of limitation in Place50 ULP by doing the auto-placement by group, and having user defined position scaling and offset.

To use Group-aps_v4 ULP first download it from Autodesk website. Before running it in the schematic editor, you need to define a group of parts first.

Group-aps_v4 has a simple dialog to enter scale and offset values.

Scale is used to scale the value of original position (X and Y) of the parts in the defined group in the schematic. While X,Y offset is used to offset the final position of the part in the board after scaling it. For example, if scale was 0.5 and the position (in mil) for the part is (500,100) then is will be considered as (250,50).

Group-aps_v4 ULP originally places the group in the calculated position of the the first part. So as an output, all parts will have the same X and Y and that’s not effective. So i made a simple edit to the ULP to solve this issue. You can download the updated version N_group-aps_v4.ulp.

Exploring Eagle CAD ULPs #5 – Place50.ULP Place All Parts of The Board to The Position in The Schematic

Welcome to the 5th post of the “Exploring Eagle CAD ULPs” series. Each post will be about one  useful ULP in Eagle CAD.

“ULP” User Language Program is a plain text file which is written in a C­-like syntax and can be used to access the EAGLE data structures and to create a wide variety of output files. You can think about it as a plug-in for Eagle.

You can reach the posts published in this series using the following link.

In this post, we will discuss an autoplacer ULP. Normally, Eagle CAD places parts in the board without any considerations to electrical connections, and there isn’t any built-in auto-placing tool in Eagle.

Without the help of ULPs, you will need to do this task manually by moving connected parts near to each other. However, some ULPs can solve this problem ــ manual placement is a time consuming task when the PC can help us !.

Place50 ULP has a simple and smart idea. It’s an autoplacer which places all parts of the board to the position in the schematic. To use this ULP first download it from Autodesk website to run it in schematic. Running this ULP from schematic editor will generate a script file in your home directory. Now open board editor and run the script file “place.scr”.

I made a little edit to the original ULP to make the script file be saved in the same directory of the project rather than the home directory. Download it from here.

A simple and reliable programming & test jig

Pieter @ piconomix.com tipped us with his latest build. Check it out on the link below.

I recently had to create a programming jig for an ATmega328PB based board. 1mm diameter test pads were placed on the bottom of the PCB to give access to the ISP pins. Normally one would add two 3mm diameter holes to locate the PCB on the jig, but this PCB was too small and only had two indents on each side to keep it in place

A simple and reliable programming & test jig – [Link]