Titanium Ti60 FPGA Devices

Titanium Ti60 FPGA Devices

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Efinix’s FPGA devices feature innovative Quantum™ compute fabric with enhanced computing capability

Efinix’s Titanium FPGAs are fabricated on a 16 nm process and deliver high performance with the lowest possible power in a small physical size. With a wide range of logic element (LE) densities from 35,000 to 1 million, and compatibility with Efinix’s RISC-V SoC (system on chip) cores, they help turn a tiny chip into an accelerated embedded computing system. The Quantum computing fabric in the Titanium TI60 FPGA is made up of configurable tiles, the eXchangeable logic and routing (XLR) cell that optimizes routing efficiency, and speed while achieving high utilization ratios. The fabric also has highly configurable 10 K embedded memory blocks along with dedicated, high-speed DSP blocks. Together, these features deliver optimum performance for a wide array of applications from edge computing to industrial automation and video processing. The 16 nm process node gives Titanium FPGAs a small footprint with low power consumption, making them ideal for highly integrated applications.

The powerful I/Os of these Titanium devices allow the user to interface to processors or camera sensors with MIPI CSI-2/DSI or traditional LVDS. The high-performance fabric supports processing capability using personalized RTL algorithms or a soft RISC-V processor for a more traditional approach. Combining the two methodologies for RISC-V acceleration or custom instructions allows optimized performance, cost, and power.

The Ti60W64 is unique as it is only 3.5 mm x 3.5 mm and still holds 60,000 logic elements.

For further space constraints, use the system-architected F100 BGA device that includes the same Ti60 as well as configuration Flash and HyperRAM memory. This product is truly a highly configurable SoC.

Features

  • 62,000 logic elements
  • 93 18×19 DSP blocks (“fracturable” to perform smaller multiply functions)
  • 2.62 MB embedded block RAM
  • Four PLLs
  • 146 high-speed I/O (HSIO) pins that can be used for MIPI D-PHY lanes for CSI-2 and DSI TX/RX
  • 34 high-voltage I/O (HVIO) pins for interfacing with 3.3 V interfaces
  • Support for AES-GCM-256 bitstream encryption and RSA-4096 bitstream authentication for secure systems
  • Soft error detection block
  • Footprint: 10 mm x 10 mm (BGA225), 5.5 mm x 5.5 mm (BGA100), or 3.5 mm x 3.4 mm (WLCSP64)

more information: https://www.efinixinc.com/products-titanium.html

About mixos

Mike is the founder and editor of Electronics-Lab.com, an electronics engineering community/news and project sharing platform. He studied Electronics and Physics and enjoys everything that has moving electrons and fun. His interests lying on solar cells, microcontrollers and switchmode power supplies. Feel free to reach him for feedback, random tips or just to say hello :-)

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